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Add Unsigned Bitvector Division #136

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Add Unsigned Bitvector Division #136

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9a2622a
Add udiv_bits primitive
ncough Apr 16, 2025
23d0cb2
Whitespace on transforms
ncough Apr 16, 2025
3e13ac5
Merge branch 'partial_eval' into div
ncough Apr 16, 2025
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2 changes: 2 additions & 0 deletions libASL/rASL_check.ml
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Original file line number Diff line number Diff line change
Expand Up @@ -114,6 +114,7 @@ module AllowedIntrinsics = struct
FIdent("slt_bits",0);
FIdent("sle_bits",0);
FIdent("sdiv_bits",0);
FIdent("udiv_bits",0);
FIdent("ite",0);
FIdent("eq_bool",0);
FIdent("ne_bool",0);
Expand Down Expand Up @@ -143,6 +144,7 @@ module AllowedIntrinsics = struct
FIdent("sub_vec",0);
FIdent("mul_vec",0);
FIdent("sdiv_vec",0);
FIdent("udiv_vec",0);
FIdent("lsr_vec",0);
FIdent("asr_vec",0);
FIdent("lsl_vec",0);
Expand Down
2 changes: 1 addition & 1 deletion libASL/scala_backend.ml
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Expand Up @@ -59,7 +59,7 @@ module StringSet = Set.Make(String)
"f_gen_load"; "f_gen_SignExtend"; "f_gen_ZeroExtend"; "f_gen_add_bits";
"f_gen_and_bits"; "f_gen_and_bool"; "f_gen_asr_bits"; "f_gen_lsl_bits";
"f_gen_lsr_bits"; "f_gen_mul_bits"; "f_gen_ne_bits"; "f_gen_not_bits";
"f_gen_not_bool"; "f_gen_or_bits"; "f_gen_or_bool"; "f_gen_sdiv_bits";
"f_gen_not_bool"; "f_gen_or_bits"; "f_gen_or_bool"; "f_gen_sdiv_bits"; "f_gen_udiv_bits";
"f_gen_sle_bits"; "f_gen_slt_bits"; "f_gen_sub_bits";
"f_gen_AArch64_MemTag_read"; "f_gen_AArch64_MemTag_set"; "f_gen_Mem_read"; "f_gen_slice";
"f_gen_replicate_bits"; "f_gen_append_bits"; "f_gen_array_load";
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2 changes: 2 additions & 0 deletions libASL/symbolic.ml
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Expand Up @@ -942,6 +942,7 @@ let prims_pure () =
FIdent("slt_bits",0);
FIdent("sle_bits",0);
FIdent("sdiv_bits",0);
FIdent("udiv_bits",0);
FIdent("ite",0);
] @ (if !use_vectoriser then [
FIdent("Elem.set",0);
Expand All @@ -950,6 +951,7 @@ let prims_pure () =
FIdent("sub_vec",0);
FIdent("mul_vec",0);
FIdent("sdiv_vec",0);
FIdent("udiv_vec",0);
FIdent("lsr_vec",0);
FIdent("asr_vec",0);
FIdent("lsl_vec",0);
Expand Down
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