Bump Chisel and rocket-chip (#65)

Makefile

@@ -1,6 +1,6 @@
 init:
 	git submodule update --init
-	cd rocket-chip && git submodule update --init hardfloat api-config-chipsalliance
+	cd rocket-chip && git submodule update --init hardfloat cde
 
 compile:
 	mill -i CoupledL2.compile

build.sc

@@ -4,12 +4,12 @@ import scalafmt._
 import os.Path
 import publish._
 import $file.`rocket-chip`.common
-import $file.`rocket-chip`.`api-config-chipsalliance`.`build-rules`.mill.build
+import $file.`rocket-chip`.cde.common
 import $file.`rocket-chip`.hardfloat.build
 
 val defaultVersions = Map(
-  "chisel3" -> "3.5.0",
-  "chisel3-plugin" -> "3.5.0",
+  "chisel3" -> "3.5.4",
+  "chisel3-plugin" -> "3.5.4",
   "chiseltest" -> "0.3.2",
   "scala" -> "2.12.13",
   "scalatest" -> "3.2.7"
@@ -29,7 +29,7 @@ trait CommonModule extends ScalaModule {
   override def scalacOptions = Seq("-Xsource:2.11")
 
   val macroParadise = ivy"org.scalamacros:::paradise:2.1.1"
-  val chisel3Plugin = ivy"edu.berkeley.cs:::chisel3-plugin:3.5.0"
+  val chisel3Plugin = ivy"edu.berkeley.cs:::chisel3-plugin:3.5.4"
 
   override def compileIvyDeps = Agg(macroParadise)
   override def scalacPluginIvyDeps = Agg(macroParadise, chisel3Plugin)
@@ -46,8 +46,8 @@ object rocketchip extends `rocket-chip`.common.CommonRocketChip {
 
   override def millSourcePath = rcPath
 
-  object configRocket extends `rocket-chip`.`api-config-chipsalliance`.`build-rules`.mill.build.config with PublishModule {
-    override def millSourcePath = rcPath / "api-config-chipsalliance" / "design" / "craft"
+  object cdeRocket extends `rocket-chip`.cde.common.CDEModule with PublishModule {
+    override def millSourcePath = rcPath / "cde" / "cde"
 
     override def scalaVersion = T {
       rocketchip.scalaVersion()
@@ -70,21 +70,21 @@ object rocketchip extends `rocket-chip`.common.CommonRocketChip {
     }
 
     def chisel3IvyDeps = if(chisel3Module.isEmpty) Agg(
-      common.getVersion("chisel3")
+      `rocket-chip`.common.getVersion("chisel3")
     ) else Agg.empty[Dep]
 
-    def chisel3PluginIvyDeps = Agg(common.getVersion("chisel3-plugin", cross=true))
+    def chisel3PluginIvyDeps = Agg(`rocket-chip`.common.getVersion("chisel3-plugin", cross=true))
   }
 
   def hardfloatModule = hardfloatRocket
 
-  def configModule = configRocket
+  def cdeModule = cdeRocket
 
 }
 
 object utility extends SbtModule with ScalafmtModule with CommonModule {
 
-   override def ivyDeps = Agg(common.getVersion("chisel3"))
+   override def ivyDeps = Agg(`rocket-chip`.common.getVersion("chisel3"))
 
    override def millSourcePath = os.pwd / "utility"
 

src/main/scala/coupledL2/AcquireUnit.scala

@@ -22,7 +22,7 @@ import chisel3.util._
 import utility._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import huancun.{PreferCacheKey}
 
 class AcquireUnit(implicit p: Parameters) extends L2Module {

src/main/scala/coupledL2/Common.scala

@@ -19,7 +19,7 @@ package coupledL2
 
 import chisel3._
 import chisel3.util._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tilelink.TLPermissions._
 import utility.MemReqSource
 
@@ -176,7 +176,7 @@ class MSHRInfo(implicit p: Parameters) extends L2Bundle {
   // to drop duplicate prefetch reqs
   val isAcqOrPrefetch = Bool()
   val isPrefetch = Bool()
-  
+
   // whether the mshr_task already in mainpipe
   val s_refill = Bool()
   val mergeA = Bool() // whether the mshr already merge an acquire(avoid alias merge)

src/main/scala/coupledL2/CoupledL2.scala

@@ -26,7 +26,7 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
 import freechips.rocketchip.util._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import scala.math.max
 import coupledL2.prefetch._
 import coupledL2.utils.XSPerfAccumulate
@@ -315,13 +315,13 @@ class CoupledL2(implicit p: Parameters) extends LazyModule with HasCoupledL2Para
       case (((in, edgeIn), (out, edgeOut)), i) =>
         require(in.params.dataBits == out.params.dataBits)
         val rst_L2 = reset
-        val slice = withReset(rst_L2) { 
+        val slice = withReset(rst_L2) {
           Module(new Slice()(p.alterPartial {
             case EdgeInKey  => edgeIn
             case EdgeOutKey => edgeOut
             case BankBitsKey => bankBits
             case SliceIdKey => i
-          })) 
+          }))
         }
         val sourceD_can_go = RegNextN(!hint_fire || i.U === OHToUInt(hint_chosen), hintCycleAhead - 1)
         release_sourceD_condition(i) := sourceD_can_go && !slice.io.in.d.valid

src/main/scala/coupledL2/CustomL1Hint.scala

@@ -20,7 +20,7 @@ package coupledL2
 import chisel3._
 import chisel3.util._
 import utility._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tilelink.TLMessages._
 import coupledL2.utils._
 
@@ -88,7 +88,7 @@ class CustomL1Hint(implicit p: Parameters) extends L2Module {
   val s4_l2_hit_grant_data = task_s4.valid && req_grantbuffer_next_cycle_s4 && task_s4.bits.opcode === GrantData && task_s4.bits.fromA && !task_s4.bits.mshrTask && !task_s4.bits.fromL2pft.getOrElse(false.B)
 
   val hint_s1, hint_s2, hint_s3, hint_s4, hint_s5 = Wire(io.l1Hint.cloneType)
-  
+
   // S1 hint
   //    * l1 acquire and l2 miss situation, **no hit situation**
   val s1_l2_miss_refill_grant_data    = task_s1.valid && task_s1.bits.fromA && task_s1.bits.opcode === GrantData
@@ -185,8 +185,8 @@ class CustomL1Hint(implicit p: Parameters) extends L2Module {
   // S4 hint
   //    * l1 acquire and l2 miss situation
   val s4_l2_miss_refill_grant_data    = d_s4 && task_s4.bits.opcode === GrantData && task_s4.bits.fromA && task_s4.bits.mshrTask && !task_s4.bits.fromL2pft.getOrElse(false.B)
-  val s4_l2_miss_refill_counter_match = Mux(d_s5 && task_s5.bits.opcode(0), (globalCounter + 3.U) === hintCycleAhead.U, 
-                                            Mux(d_s5 && !task_s5.bits.opcode(0), (globalCounter + 2.U) === hintCycleAhead.U, 
+  val s4_l2_miss_refill_counter_match = Mux(d_s5 && task_s5.bits.opcode(0), (globalCounter + 3.U) === hintCycleAhead.U,
+                                            Mux(d_s5 && !task_s5.bits.opcode(0), (globalCounter + 2.U) === hintCycleAhead.U,
                                                 (globalCounter + 1.U) === hintCycleAhead.U ))
   val validHintMiss_s4 = s4_l2_miss_refill_grant_data && s4_l2_miss_refill_counter_match
 

src/main/scala/coupledL2/DataStorage.scala

@@ -21,7 +21,7 @@ import chisel3._
 import chisel3.util._
 import coupledL2.utils.SRAMTemplate
 import utility.RegNextN
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 
 class DSRequest(implicit p: Parameters) extends L2Bundle {
   val way = UInt(wayBits.W)
@@ -50,7 +50,7 @@ class DataStorage(implicit p: Parameters) extends L2Module {
     gen = new DSBlock,
     set = blocks,
     way = 1,
-    singlePort = true 
+    singlePort = true
   ))
 
   val arrayIdx = Cat(io.req.bits.way, io.req.bits.set)

src/main/scala/coupledL2/Directory.scala

@@ -22,7 +22,7 @@ import chisel3.util._
 import freechips.rocketchip.util.SetAssocLRU
 import coupledL2.utils._
 import utility.{ParallelPriorityMux, RegNextN}
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import coupledL2.prefetch.PfSource
 import freechips.rocketchip.tilelink.TLMessages._
 

src/main/scala/coupledL2/GrantBuffer.scala

@@ -20,7 +20,7 @@ package coupledL2
 import chisel3._
 import chisel3.util._
 import utility._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
 import coupledL2.prefetch.PrefetchResp
@@ -242,7 +242,7 @@ class GrantBuffer(implicit p: Parameters) extends L2Module {
   }
 
   io.e.ready := true.B
- 
+
   // =========== handle blocking - capacity conflict ===========
   // count the number of valid blocks + those in pipe that might use GrantBuf
   // so that GrantBuffer will not exceed capacity [back pressure]

src/main/scala/coupledL2/L2Param.scala

@@ -14,15 +14,15 @@
   * See the Mulan PSL v2 for more details.
   * *************************************************************************************
   */
-  
+
 package coupledL2
 
 import chisel3._
 import chisel3.util.log2Ceil
 import freechips.rocketchip.diplomacy.BufferParams
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
-import chipsalliance.rocketchip.config.Field
+import org.chipsalliance.cde.config.Field
 import huancun.CacheParameters
 import coupledL2.prefetch._
 import utility.{MemReqSource, ReqSourceKey}
@@ -114,7 +114,7 @@ case class L2Param
 
   // Client (these are set in Configs.scala in XiangShan)
   echoField: Seq[BundleFieldBase] = Nil,
-  reqField: Seq[BundleFieldBase] = Nil, 
+  reqField: Seq[BundleFieldBase] = Nil,
   respKey: Seq[BundleKeyBase] = Seq(IsHitKey),
   // Manager
   reqKey: Seq[BundleKeyBase] = Seq(AliasKey, VaddrKey, PrefetchKey, ReqSourceKey),

src/main/scala/coupledL2/MSHR.scala

@@ -24,7 +24,7 @@ import utility.{MemReqSource, ParallelLookUp, ParallelPriorityMux}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
 import freechips.rocketchip.tilelink.TLPermissions._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import coupledL2.prefetch.{PfSource, PrefetchTrain}
 import coupledL2.utils.XSPerfAccumulate
 
@@ -540,7 +540,7 @@ class MSHR(implicit p: Parameters) extends L2Module {
   when (req_valid) {
     timer := timer + 1.U
   }
-  
+
   val no_schedule = state.s_refill && state.s_probeack && state.s_merge_probeack && state.s_release // && state.s_triggerprefetch.getOrElse(true.B)
   val no_wait = state.w_rprobeacklast && state.w_pprobeacklast && state.w_grantlast && state.w_releaseack && state.w_replResp
   val will_free = no_schedule && no_wait

src/main/scala/coupledL2/MSHRBuffer.scala

@@ -19,7 +19,7 @@ package coupledL2
 
 import chisel3._
 import chisel3.util._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import coupledL2.utils._
 import java.util.ResourceBundle
 

src/main/scala/coupledL2/MSHRCtl.scala

@@ -20,7 +20,7 @@ package coupledL2
 import chisel3._
 import chisel3.util._
 import utility._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
 import coupledL2.prefetch.PrefetchTrain
@@ -69,7 +69,7 @@ class MSHRCtl(implicit p: Parameters) extends L2Module {
       val sinkD = new RespBundle
       val sourceC = new RespBundle
     })
-    
+
     val releaseBufWriteId = Output(UInt(mshrBits.W))
 
     /* nested writeback */
@@ -184,7 +184,7 @@ class MSHRCtl(implicit p: Parameters) extends L2Module {
   //   _ =>
   //     XSPerfAccumulate(cacheParams, "prefetch_trains", io.prefetchTrain.get.fire)
   // }
-  
+
   if (cacheParams.enablePerf) {
     val start = 0
     val stop = 100

src/main/scala/coupledL2/MainPipe.scala

@@ -21,7 +21,7 @@ import chisel3._
 import chisel3.util._
 import utility._
 import coupledL2.MetaData._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
 import freechips.rocketchip.tilelink.TLPermissions._
@@ -488,7 +488,7 @@ class MainPipe(implicit p: Parameters) extends L2Module {
 
   customL1Hint.io.s1 := io.taskInfo_s1
   customL1Hint.io.s2 := task_s2
-  
+
   customL1Hint.io.s3.task      := task_s3
   customL1Hint.io.s3.d         := d_s3.valid
   customL1Hint.io.s3.need_mshr := need_mshr_s3

src/main/scala/coupledL2/ProbeQueue.scala

@@ -21,7 +21,7 @@ import chisel3._
 import chisel3.util._
 import coupledL2.utils._
 import freechips.rocketchip.tilelink._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 
 class ProbeQueue(implicit p: Parameters) extends L2Module {
   val io = IO(new Bundle() {

src/main/scala/coupledL2/RefillUnit.scala

@@ -21,7 +21,7 @@ import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import coupledL2.utils.XSPerfAccumulate
 
 class grantAckQEntry(implicit p: Parameters) extends L2Bundle {

src/main/scala/coupledL2/RequestArb.scala

@@ -22,7 +22,7 @@ import chisel3.util._
 import utility._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import coupledL2.utils.XSPerfAccumulate
 
 class RequestArb(implicit p: Parameters) extends L2Module {
@@ -201,7 +201,7 @@ class RequestArb(implicit p: Parameters) extends L2Module {
   XSPerfAccumulate(cacheParams, "sinkA_req", io.sinkA.fire)
   XSPerfAccumulate(cacheParams, "sinkB_req", io.sinkB.fire)
   XSPerfAccumulate(cacheParams, "sinkC_req", io.sinkC.fire)
-  
+
   XSPerfAccumulate(cacheParams, "sinkA_stall", io.sinkA.valid && !io.sinkA.ready)
   XSPerfAccumulate(cacheParams, "sinkB_stall", io.sinkB.valid && !io.sinkB.ready)
   XSPerfAccumulate(cacheParams, "sinkC_stall", io.sinkC.valid && !io.sinkC.ready)

src/main/scala/coupledL2/RequestBuffer.scala

@@ -1,6 +1,6 @@
 package coupledL2
 
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tilelink.TLMessages._
 import chisel3._
 import chisel3.util._

src/main/scala/coupledL2/SinkA.scala

@@ -19,7 +19,7 @@ package coupledL2
 
 import chisel3._
 import chisel3.util._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
 import freechips.rocketchip.tilelink.TLHints._

src/main/scala/coupledL2/SinkB.scala

@@ -19,7 +19,7 @@ package coupledL2
 
 import chisel3._
 import chisel3.util._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
 import freechips.rocketchip.tilelink.TLPermissions._

src/main/scala/coupledL2/SinkC.scala

@@ -21,7 +21,7 @@ import chisel3._
 import chisel3.util._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import coupledL2.utils.XSPerfAccumulate
 import utility.MemReqSource
 
@@ -48,7 +48,7 @@ class SinkC(implicit p: Parameters) extends L2Module {
     val refillBufWrite = Flipped(new MSHRBufWrite)
     val msInfo = Vec(mshrsAll, Flipped(ValidIO(new MSHRInfo)))
   })
-  
+
   val (first, last, _, beat) = edgeIn.count(io.c)
   val isRelease = io.c.bits.opcode(1)
   val hasData = io.c.bits.opcode(0)

src/main/scala/coupledL2/Slice.scala

@@ -22,7 +22,7 @@ import chisel3.util._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
 import freechips.rocketchip.util.leftOR
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import coupledL2.utils._
 import coupledL2.debug._
 import coupledL2.prefetch.PrefetchIO

src/main/scala/coupledL2/SourceB.scala

@@ -22,7 +22,7 @@ import chisel3._
 import chisel3.util._
 import coupledL2.utils._
 import freechips.rocketchip.tilelink._
-import chipsalliance.rocketchip.config.Parameters
+import org.chipsalliance.cde.config.Parameters
 import utility._
 
 class GrantStatus(implicit p: Parameters) extends L2Bundle {