fix prefetch settings (#64)

* prefetch: fix bug in parameters * prefetch: add Stream and Stride parameters
OpenXiangShan · Oct 7, 2023 · d26711d · d26711d
1 parent 92685fc
commit d26711d
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Showing 2 changed files with 42 additions and 2 deletions.
diff --git a/src/main/scala/coupledL2/TopDownMonitor.scala b/src/main/scala/coupledL2/TopDownMonitor.scala
@@ -115,6 +115,8 @@ class TopDownMonitor()(implicit p: Parameters) extends L2Module {
     r =>  !r.hit &&
       (r.replacerInfo.reqSource === MemReqSource.Prefetch2L2BOP.id.U ||
        r.replacerInfo.reqSource === MemReqSource.Prefetch2L2SMS.id.U ||
+       r.replacerInfo.reqSource === MemReqSource.Prefetch2L2Stride.id.U ||
+       r.replacerInfo.reqSource === MemReqSource.Prefetch2L2Stream.id.U ||
        r.replacerInfo.reqSource === MemReqSource.Prefetch2L2TP.id.U)
   )
   val l2prefetchSentBOP = dirResultMatchVec(
@@ -123,6 +125,12 @@ class TopDownMonitor()(implicit p: Parameters) extends L2Module {
   val l2prefetchSentSMS = dirResultMatchVec(
     r => !r.hit && r.replacerInfo.reqSource === MemReqSource.Prefetch2L2SMS.id.U
   )
+  val l2prefetchSentStride = dirResultMatchVec(
+    r => !r.hit && r.replacerInfo.reqSource === MemReqSource.Prefetch2L2Stride.id.U
+  )
+  val l2prefetchSentStream = dirResultMatchVec(
+    r => !r.hit && r.replacerInfo.reqSource === MemReqSource.Prefetch2L2Stream.id.U
+  )
   val l2prefetchSentTP = dirResultMatchVec(
     r => !r.hit && r.replacerInfo.reqSource === MemReqSource.Prefetch2L2TP.id.U
   )
@@ -138,6 +146,14 @@ class TopDownMonitor()(implicit p: Parameters) extends L2Module {
     r => reqFromCPU(r) && r.hit &&
       r.meta.prefetch.getOrElse(false.B) && r.meta.prefetchSrc.getOrElse(PfSource.NoWhere.id.U) === PfSource.SMS.id.U
   )
+  val l2prefetchUsefulStride = dirResultMatchVec(
+    r => reqFromCPU(r) && r.hit &&
+      r.meta.prefetch.getOrElse(false.B) && r.meta.prefetchSrc.getOrElse(PfSource.NoWhere.id.U) === PfSource.Stride.id.U
+  )
+  val l2prefetchUsefulStream = dirResultMatchVec(
+    r => reqFromCPU(r) && r.hit &&
+      r.meta.prefetch.getOrElse(false.B) && r.meta.prefetchSrc.getOrElse(PfSource.NoWhere.id.U) === PfSource.Stream.id.U
+  )
   val l2prefetchUsefulTP = dirResultMatchVec(
     r => reqFromCPU(r) && r.hit &&
       r.meta.prefetch.getOrElse(false.B) && r.meta.prefetchSrc.getOrElse(PfSource.NoWhere.id.U) === PfSource.TP.id.U
@@ -163,6 +179,16 @@ class TopDownMonitor()(implicit p: Parameters) extends L2Module {
     PopCount(l2prefetchUsefulSMS), PopCount(l2prefetchSentSMS),
     1000, clock, reset
   )
+  XSPerfRolling(
+    cacheParams, "L2PrefetchAccuracyStride",
+    PopCount(l2prefetchUsefulStride), PopCount(l2prefetchSentStride),
+    1000, clock, reset
+  )
+  XSPerfRolling(
+    cacheParams, "L2PrefetchAccuracyStream",
+    PopCount(l2prefetchUsefulStream), PopCount(l2prefetchSentStream),
+    1000, clock, reset
+  )
   XSPerfRolling(
     cacheParams, "L2PrefetchAccuracyTP",
     PopCount(l2prefetchUsefulTP), PopCount(l2prefetchSentTP),
@@ -188,6 +214,16 @@ class TopDownMonitor()(implicit p: Parameters) extends L2Module {
     PopCount(l2prefetchUsefulSMS), PopCount(l2demandRequest),
     1000, clock, reset
   )
+  XSPerfRolling(
+    cacheParams, "L2PrefetchCoverageStride",
+    PopCount(l2prefetchUsefulStride), PopCount(l2demandRequest),
+    1000, clock, reset
+  )
+  XSPerfRolling(
+    cacheParams, "L2PrefetchCoverageStream",
+    PopCount(l2prefetchUsefulStream), PopCount(l2demandRequest),
+    1000, clock, reset
+  )
   XSPerfRolling(
     cacheParams, "L2PrefetchCoverageTP",
     PopCount(l2prefetchUsefulTP), PopCount(l2demandRequest),

diff --git a/src/main/scala/coupledL2/prefetch/PrefetchParameters.scala b/src/main/scala/coupledL2/prefetch/PrefetchParameters.scala
@@ -40,6 +40,8 @@ object PfSource extends Enumeration {
   val NoWhere = Value("NoWhere")
   val SMS     = Value("SMS")
   val BOP     = Value("BOP")
+  val Stream  = Value("Stream")
+  val Stride  = Value("Stride")
   val TP      = Value("TP")
 
   val PfSourceCount = Value("PfSourceCount")
@@ -48,9 +50,11 @@ object PfSource extends Enumeration {
   def fromMemReqSource(s: UInt): UInt = {
     val pfsrc = WireInit(NoWhere.id.U.asTypeOf(UInt(pfSourceBits.W)))
     switch(s) {
-      is (MemReqSource.Prefetch2L2BOP.id.U) { pfsrc := SMS.id.U }
-      is (MemReqSource.Prefetch2L2SMS.id.U) { pfsrc := BOP.id.U }
+      is (MemReqSource.Prefetch2L2BOP.id.U) { pfsrc := BOP.id.U }
+      is (MemReqSource.Prefetch2L2SMS.id.U) { pfsrc := SMS.id.U }
       is (MemReqSource.Prefetch2L2TP.id.U)  { pfsrc := TP.id.U  }
+      is (MemReqSource.Prefetch2L2Stream.id.U) { pfsrc := Stream.id.U }
+      is (MemReqSource.Prefetch2L2Stride.id.U) { pfsrc := Stride.id.U }
     }
     pfsrc
   }