Skip to content

Commit

Permalink
Merge pull request #43 from arturum1/main
Browse files Browse the repository at this point in the history 
Remove axi2axil converters for clint and plic; Update reset address to 0x40000000.
  • Loading branch information
@jjts
jjts authored Sep 19, 2024
2 parents 4478da7 + 67b1f13 commit a522777
Show file tree
Hide file tree
Showing 5 changed files with 48 additions and 105 deletions.
8 changes: 5 additions & 3 deletions Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,12 +8,14 @@ VEX_SUBMODULES_DIR:=$(VEXRISCV_DIR)/submodules
.PHONY: vexriscv clean-all qemu

CPU ?= VexRiscvAxi4LinuxPlicClint
JDK_HOME := $(shell dirname $$(dirname $$(which java)))

# Primary targets
vexriscv:
cp $(VEX_HARDWARE_DIR)/vexriscv_core/* $(VEX_SUBMODULES_DIR)/VexRiscv/src/main/scala/vexriscv/demo/ && \
cd submodules/VexRiscv && sbt "runMain vexriscv.demo.$(CPU)" && \
cp $(CPU).v $(VEXRISCV_SRC_DIR)
cp $(VEX_HARDWARE_DIR)/vexriscv_core/* $(VEX_SUBMODULES_DIR)/VexRiscv/src/main/scala/vexriscv/demo/
cd submodules/VexRiscv && \
sbt -java-home $(JDK_HOME) "runMain vexriscv.demo.$(CPU)" && \
cp $(CPU).v $(VEXRISCV_SRC_DIR)

#
# Clean
Expand Down
2 changes: 0 additions & 2 deletions default.nix
View file

This file was deleted.

4 changes: 2 additions & 2 deletions hardware/src/VexRiscvAxi4LinuxPlicClint.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6754,11 +6754,11 @@ module VexRiscvAxi4LinuxPlicClint (
assign utime = clintCtrl_io_time;
always @(posedge clk or posedge reset) begin
if(reset) begin
IBusCachedPlugin_fetchPc_pcReg <= 32'h80000000;
IBusCachedPlugin_fetchPc_pcReg <= 32'h40000000;
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
IBusCachedPlugin_fetchPc_booted <= 1'b0;
IBusCachedPlugin_fetchPc_inc <= 1'b0;
IBusCachedPlugin_decodePc_pcReg <= 32'h80000000;
IBusCachedPlugin_decodePc_pcReg <= 32'h40000000;
_zz_IBusCachedPlugin_iBusRsp_stages_1_input_valid_1 <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
IBusCachedPlugin_decompressor_bufferValid <= 1'b0;
Expand Down
1 change: 1 addition & 0 deletions hardware/vexriscv_core/VexRiscvAxi4LinuxPlicClint.scala
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@ object VexRiscvAxi4LinuxPlicClint{
val cpuConfig = VexRiscvConfig(
plugins = List(
new IBusCachedPlugin(
resetVector = 0x40000000l,
prediction = NONE,
compressedGen = true,
injectorStage = true,
Expand Down
138 changes: 40 additions & 98 deletions iob_vexriscv.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -87,7 +87,7 @@ def setup(py_params_dict):
"name": "clint_cbus",
"descr": "CLINT CSRs bus",
"interface": {
"type": "axi",
"type": "axil",
"subtype": "slave",
"port_prefix": "clint_",
"ID_W": "AXI_ID_W",
Expand All @@ -100,7 +100,7 @@ def setup(py_params_dict):
"name": "plic_cbus",
"descr": "PLIC CSRs bus",
"interface": {
"type": "axi",
"type": "axil",
"subtype": "slave",
"port_prefix": "plic_",
"ID_W": "AXI_ID_W",
Expand Down Expand Up @@ -148,110 +148,52 @@ def setup(py_params_dict):
{"name": "dbus_axi_arlock_int", "width": "1"},
],
},
{
"name": "clint_cbus_axil",
"descr": "CLINT CSRs bus",
"interface": {
"type": "axil",
"subtype": "slave",
"wire_prefix": "clint_",
"ID_W": "AXI_ID_W",
"ADDR_W": "16",
"DATA_W": "AXI_DATA_W",
"LEN_W": "AXI_LEN_W",
},
},
{
"name": "plic_cbus_axil",
"descr": "PLIC CSRs bus",
"interface": {
"type": "axil",
"subtype": "slave",
"wire_prefix": "plic_",
"ID_W": "AXI_ID_W",
"ADDR_W": "22",
"DATA_W": "AXI_DATA_W",
"LEN_W": "AXI_LEN_W",
},
},
],
"blocks": [
{
"core_name": "axi2axil",
"instance_name": "clint_axi2axil",
"instance_description": "Convert AXI to AXI lite for CLINT",
"parameters": {
"AXI_ID_W": "AXI_ID_W",
"AXI_ADDR_W": "16",
"AXI_DATA_W": "AXI_DATA_W",
"AXI_LEN_W": "AXI_LEN_W",
},
"connect": {
"axi": "clint_cbus",
"axil": "clint_cbus_axil",
},
},
{
"core_name": "axi2axil",
"instance_name": "plic_axi2axil",
"instance_description": "Convert AXI to AXI lite for PLIC",
"parameters": {
"AXI_ID_W": "AXI_ID_W",
"AXI_ADDR_W": "22",
"AXI_DATA_W": "AXI_DATA_W",
"AXI_LEN_W": "AXI_LEN_W",
},
"connect": {
"axi": "plic_cbus",
"axil": "plic_cbus_axil",
},
},
],
"snippets": [
{
"verilog_code": """
// Instantiation of VexRiscv, Plic, and Clint
VexRiscvAxi4LinuxPlicClint CPU (
// CLINT
.clint_awvalid(clint_axil_awvalid),
.clint_awready(clint_axil_awready),
.clint_awaddr(clint_axil_awaddr),
.clint_awprot(clint_axil_awprot),
.clint_wvalid(clint_axil_wvalid),
.clint_wready(clint_axil_wready),
.clint_wdata(clint_axil_wdata),
.clint_wstrb(clint_axil_wstrb),
.clint_bvalid(clint_axil_bvalid),
.clint_bready(clint_axil_bready),
.clint_bresp(clint_axil_bresp),
.clint_arvalid(clint_axil_arvalid),
.clint_arready(clint_axil_arready),
.clint_araddr(clint_axil_araddr),
.clint_arprot(clint_axil_arprot),
.clint_rvalid(clint_axil_rvalid),
.clint_rready(clint_axil_rready),
.clint_rdata(clint_axil_rdata),
.clint_rresp(clint_axil_rresp),
.clint_awvalid(clint_axil_awvalid_i),
.clint_awready(clint_axil_awready_o),
.clint_awaddr(clint_axil_awaddr_i),
.clint_awprot(clint_axil_awprot_i),
.clint_wvalid(clint_axil_wvalid_i),
.clint_wready(clint_axil_wready_o),
.clint_wdata(clint_axil_wdata_i),
.clint_wstrb(clint_axil_wstrb_i),
.clint_bvalid(clint_axil_bvalid_o),
.clint_bready(clint_axil_bready_i),
.clint_bresp(clint_axil_bresp_o),
.clint_arvalid(clint_axil_arvalid_i),
.clint_arready(clint_axil_arready_o),
.clint_araddr(clint_axil_araddr_i),
.clint_arprot(clint_axil_arprot_i),
.clint_rvalid(clint_axil_rvalid_o),
.clint_rready(clint_axil_rready_i),
.clint_rdata(clint_axil_rdata_o),
.clint_rresp(clint_axil_rresp_o),
// PLIC
.plic_awvalid(plic_axil_awvalid),
.plic_awready(plic_axil_awready),
.plic_awaddr(plic_axil_awaddr),
.plic_awprot(plic_axil_awprot),
.plic_wvalid(plic_axil_wvalid),
.plic_wready(plic_axil_wready),
.plic_wdata(plic_axil_wdata),
.plic_wstrb(plic_axil_wstrb),
.plic_bvalid(plic_axil_bvalid),
.plic_bready(plic_axil_bready),
.plic_bresp(plic_axil_bresp),
.plic_arvalid(plic_axil_arvalid),
.plic_arready(plic_axil_arready),
.plic_araddr(plic_axil_araddr),
.plic_arprot(plic_axil_arprot),
.plic_rvalid(plic_axil_rvalid),
.plic_rready(plic_axil_rready),
.plic_rdata(plic_axil_rdata),
.plic_rresp(plic_axil_rresp),
.plic_awvalid(plic_axil_awvalid_i),
.plic_awready(plic_axil_awready_o),
.plic_awaddr(plic_axil_awaddr_i),
.plic_awprot(plic_axil_awprot_i),
.plic_wvalid(plic_axil_wvalid_i),
.plic_wready(plic_axil_wready_o),
.plic_wdata(plic_axil_wdata_i),
.plic_wstrb(plic_axil_wstrb_i),
.plic_bvalid(plic_axil_bvalid_o),
.plic_bready(plic_axil_bready_i),
.plic_bresp(plic_axil_bresp_o),
.plic_arvalid(plic_axil_arvalid_i),
.plic_arready(plic_axil_arready_o),
.plic_araddr(plic_axil_araddr_i),
.plic_arprot(plic_axil_arprot_i),
.plic_rvalid(plic_axil_rvalid_o),
.plic_rready(plic_axil_rready_i),
.plic_rdata(plic_axil_rdata_o),
.plic_rresp(plic_axil_rresp_o),
.plicInterrupts(plic_interrupts_i),
// Instruction Bus
.iBusAxi_arvalid(ibus_axi_arvalid_o),
Expand Down

0 comments on commit a522777

Please sign in to comment.