riscv-mcu

中文

Directory Introduction

1. netlist: there are CPU designs based on the digital software, created through wiring methods, along with the corresponding boot and test codes. This part is finalized and will no longer be updated. For specific introductions, see: riscv-digital.
2. verilog: there is RISC-V CPU code developed in Verilog, which is continuously being updated.
3. digital_soc: there is a SoC built with CPU modules written in Verilog using the digital software, which can be run through digital simulation.
4. fpga_soc: there is a SoC constructed with RISC-V CPU modules based on FPGA. This has not yet started, with the goal being to run the CPU IP implemented in Verilog on an FPGA development board.

digital_soc Introduction

1. Generating Bootloader and Test Program Hex Files

The bootloader and test program code are located in the digital_soc/src directory. To generate the hex files for the bootloader and test program, execute the following commands within that directory:

    make; python3 ./mkhex.py

2. Verilog Simulation
For Verilog simulation, follow these steps:

• Navigate to the verilog directory.
• Execute the following command to build the simulation:

./make.bat digital_soc 

• After the build is complete, run the simulation waveform viewer using:

gtkwave.exe ./digital_soc.vcd 

This will allow you to view the simulation waveforms generated by the Verilog simulation.

3. Digital Simulation

To perform digital simulation, follow these steps:

• Open the Digital software.
• Load the digital_soc/digital/digital_soc.dig file.
• Before running the simulation, you need to configure the riscvmcu component:
  • Right-click on the riscvmcu component.
  • In the context menu, select the Options tab.
  • Locate the iverilog option.
  • Modify the dependency path to match the corresponding path on your local machine.
• Save the changes and close the configuration window.
• Run the simulation.