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same70b: Add support for SMC for SAME70-series #78120

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6 changes: 5 additions & 1 deletion drivers/memc/memc_sam_smc.c
Original file line number Diff line number Diff line change
Expand Up @@ -75,17 +75,21 @@
SMC_CYCLE_NWE_CYCLE(DT_PROP_BY_IDX(node_id, atmel_smc_cycle_timing, 0)) \
| SMC_CYCLE_NRD_CYCLE(DT_PROP_BY_IDX(node_id, atmel_smc_cycle_timing, 1))

#define BUS_WIDTH(node_id) COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_bus_width), \
(SMC_MODE_DBW_16_BIT), (0))

#define BANK_CONFIG(node_id) \
{ \
.cs = DT_REG_ADDR(node_id), \
.mode = COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_write_mode), \
.mode = BUS_WIDTH(node_id) \
| COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_write_mode), \
(SMC_MODE_WRITE_MODE), (0)) \
| COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_read_mode), \
(SMC_MODE_READ_MODE), (0)), \
.setup_timing = SETUP_TIMING(node_id), \
.pulse_timing = PULSE_TIMING(node_id), \
.cycle_timing = CYCLE_TIMING(node_id), \
},

Check notice on line 92 in drivers/memc/memc_sam_smc.c

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drivers/memc/memc_sam_smc.c:92 -#define BUS_WIDTH(node_id) COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_bus_width), \ - (SMC_MODE_DBW_16_BIT), (0)) +#define BUS_WIDTH(node_id) \ + COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_bus_width), (SMC_MODE_DBW_16_BIT), (0)) -#define BANK_CONFIG(node_id) \ - { \ - .cs = DT_REG_ADDR(node_id), \ - .mode = BUS_WIDTH(node_id) \ - | COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_write_mode), \ - (SMC_MODE_WRITE_MODE), (0)) \ - | COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_read_mode), \ - (SMC_MODE_READ_MODE), (0)), \ - .setup_timing = SETUP_TIMING(node_id), \ - .pulse_timing = PULSE_TIMING(node_id), \ - .cycle_timing = CYCLE_TIMING(node_id), \ +#define BANK_CONFIG(node_id) \ + { \ + .cs = DT_REG_ADDR(node_id), \ + .mode = BUS_WIDTH(node_id) | \ + COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_write_mode), \ + (SMC_MODE_WRITE_MODE), (0)) | \ + COND_CODE_1(DT_ENUM_IDX(node_id, atmel_smc_read_mode), \ + (SMC_MODE_READ_MODE), (0)), \ + .setup_timing = SETUP_TIMING(node_id), \ + .pulse_timing = PULSE_TIMING(node_id), \ + .cycle_timing = CYCLE_TIMING(node_id), \

#define MEMC_SMC_DEFINE(inst) \
static const struct memc_smc_bank_config smc_bank_config_##inst[] = { \
Expand Down
9 changes: 9 additions & 0 deletions dts/arm/atmel/same70.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -476,6 +476,15 @@
alarms-count = <1>;
status = "disabled";
};

smc: smc@40080000 {
compatible = "atmel,sam-smc";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40080000 0x4000>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
status = "disabled";
};
};
};

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14 changes: 14 additions & 0 deletions dts/bindings/memory-controllers/atmel,sam-smc.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -148,3 +148,17 @@ child-binding:
is encoded in 9 bits where the two highest bits are multiplied
with an offset of 256.
Effective value for each element: 256 x cycle[8:7] + cycle[6:0]

atmel,smc-bus-width:
type: int
default: 8
description: |
Bus Width configuration for the Static Memory Controller that
is wired to the external device.
SMC on SAMx7 supports 8/16-bit bus width, on SAM4
only 8-bit data buses are supported.

The default value is 8-bit data buses.
enum:
- 8
- 16
2 changes: 1 addition & 1 deletion west.yml
Original file line number Diff line number Diff line change
Expand Up @@ -152,7 +152,7 @@ manifest:
groups:
- hal
- name: hal_atmel
revision: 56d60ebc909ad065bf6554cee73487969857614b
revision: pull/41/head
path: modules/hal/atmel
groups:
- hal
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