boards: enbables support for s32z270 hse crypto

Enable test for s32z270 hash crypto. Enable samples for cipher cryptoEndable samples for EBC, CBC, CTR mode of cipher crypto. Signed-off-by: Ha Duong Quang <[email protected]>
zephyrproject-rtos · Oct 9, 2024 · f861b34 · f861b34
1 parent 519a733
commit f861b34
Show file tree

Hide file tree

Showing 16 changed files with 84 additions and 1 deletion.
diff --git a/boards/nxp/s32z2xxdc2/doc/index.rst b/boards/nxp/s32z2xxdc2/doc/index.rst
@@ -59,6 +59,8 @@ The boards support the following hardware features:
 +-----------+------------+-------------------------------------+
 | LPI2C     | on-chip    | i2c                                 |
 +-----------+------------+-------------------------------------+
+| HSE       | on-chip    | crypto                              |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not currently supported by the port.
 
@@ -163,6 +165,22 @@ ADC is provided through ADC SAR controller with 2 instances. Each ADC SAR instan
 .. note::
    All channels of an instance only run on 1 group channel at the same time.
 
+CRYPTO
+======
+
+The Hardware Security Engine (HSE) supports cryptographic operations, including hashing and
+symmetric ciphers, with capabilities for ECB, CBC, and CTR modes using RAM-based key catalogs
+with 128-bit key lengths.
+
+.. note::
+   Applications must format key catalogs before executing the first service.
+   The NXP S32 HSE CRYPTO provides a Kconfig option, `CONFIG_CRYPTO_NXP_S32_HSE_FORMAT_KEY_CATALOG`,
+   which is used for testing purposes to format both the NVM and RAM key catalogs.
+
+   By default, only MU0 is activated for use by the HSE to listen for requests, while other MUs
+   remain deactivated. If applications require the use of additional MUs, they must be activated
+   beforehand.
+
 Programming and Debugging
 *************************
 

diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml
@@ -18,4 +18,5 @@ supported:
   - counter
   - adc
   - i2c
+  - crypto
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml
@@ -18,4 +18,5 @@ supported:
   - counter
   - adc
   - i2c
+  - crypto
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml
@@ -18,4 +18,5 @@ supported:
   - counter
   - adc
   - i2c
+  - crypto
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml
@@ -18,4 +18,5 @@ supported:
   - counter
   - adc
   - i2c
+  - crypto
 vendor: nxp
diff --git a/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu0.conf b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu0.conf
@@ -0,0 +1,5 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+# Only used for test
+CONFIG_CRYPTO_NXP_S32_HSE_FORMAT_KEY_CATALOG=y
diff --git a/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu0.overlay b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu0.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&mub0 {
+	status = "okay";
+};
diff --git a/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu1.conf b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu1.conf
@@ -0,0 +1,5 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+# Only used for test
+CONFIG_CRYPTO_NXP_S32_HSE_FORMAT_KEY_CATALOG=y
diff --git a/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu1.overlay b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu1.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&mub0 {
+	status = "okay";
+};
diff --git a/samples/drivers/crypto/prj.conf b/samples/drivers/crypto/prj.conf
@@ -3,4 +3,4 @@ CONFIG_CRYPTO_LOG_LEVEL_DBG=y
 CONFIG_LOG=y
 CONFIG_LOG_MODE_MINIMAL=y
 
-CONFIG_MAIN_STACK_SIZE=4096
+CONFIG_MAIN_STACK_SIZE=8192
diff --git a/samples/drivers/crypto/src/main.c b/samples/drivers/crypto/src/main.c
@@ -27,6 +27,8 @@ LOG_MODULE_REGISTER(main);
 #define CRYPTO_DEV_COMPAT st_stm32_aes
 #elif DT_HAS_COMPAT_STATUS_OKAY(nxp_mcux_dcp)
 #define CRYPTO_DEV_COMPAT nxp_mcux_dcp
+#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_s32_crypto_hse_mu)
+#define CRYPTO_DEV_COMPAT nxp_s32_crypto_hse_mu
 #elif CONFIG_CRYPTO_NRF_ECB
 #define CRYPTO_DEV_COMPAT nordic_nrf_ecb
 #elif DT_HAS_COMPAT_STATUS_OKAY(renesas_smartbond_crypto)

diff --git a/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu0.conf b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu0.conf
@@ -0,0 +1,5 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+# Only used for test
+CONFIG_CRYPTO_NXP_S32_HSE_FORMAT_KEY_CATALOG=y
diff --git a/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu0.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&mub0 {
+	status = "okay";
+};
diff --git a/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu1.conf b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu1.conf
@@ -0,0 +1,5 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+# Only used for test
+CONFIG_CRYPTO_NXP_S32_HSE_FORMAT_KEY_CATALOG=y
diff --git a/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu1.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&mub0 {
+	status = "okay";
+};
diff --git a/tests/crypto/crypto_hash/src/main.c b/tests/crypto/crypto_hash/src/main.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2022 Intel Corporation
+ * Copyright 2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,6 +14,8 @@
 #define CRYPTO_DRV_NAME CONFIG_CRYPTO_MBEDTLS_SHIM_DRV_NAME
 #elif DT_HAS_COMPAT_STATUS_OKAY(renesas_smartbond_crypto)
 #define CRYPTO_DEV_COMPAT renesas_smartbond_crypto
+#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_s32_crypto_hse_mu)
+#define CRYPTO_DEV_COMPAT nxp_s32_crypto_hse_mu
 #else
 #error "You need to enable one crypto device"
 #endif