hal: renesas: rz: Initial support for Clock Control #56
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Get clock frequency from device tree Signed-off-by: Tien Nguyen <[email protected]>
KhiemNguyenT
requested review from
soburi,
KhiemNguyenT,
thaoluonguw and
duynguyenxa
thaoluonguw
reviewed
Dec 23, 2024
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| #define BSP_CFG_CLOCK_OSCCLK_HZ DT_PROP_OR(DT_NODELABEL(oscclk), clock_frequency, 24000000) /* OSC 24000000Hz */ | ||
| #define BSP_CFG_CLOCK_PLL1_HZ (1100000000) /* PLL1 1100000000Hz */ |
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@nhutnguyenkc : I would like to confirm that OSC and PLL1 are fixed values as in HWM but the method to get value is different. OSC get from DT node, PLL1 is fixed definition. Is there any special reason here?
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@thaoluonguw , there is no special reason for it. I just thought that the BSP_CFG_CLOCK_PLL1_HZ is presenting for the frequency after PLL1 block and is the result of the calculation of OSC and PLL1. For example,
#define BSP_CFG_CLOCK_PLL1_HZ (BSP_CFG_CLOCK_OSCCLK_HZ/2)
But in case of RZ/G3S, no formula is provided, and only fixed value is showed in HWUM. Therefore, I would like to set the fixed value for it.
Please let me know if you have any suggestion.
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Support to get clock frequency from device tree