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Merge pull request YosysHQ#256 from yrabbit/prom-fix
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Fix pROM(X9).
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yrabbit authored Jul 18, 2024
2 parents 9d37e71 + 4ec4515 commit 7077e99
Showing 1 changed file with 7 additions and 1 deletion.
8 changes: 7 additions & 1 deletion apycula/gowin_pack.py
Original file line number Diff line number Diff line change
Expand Up @@ -94,7 +94,7 @@ def extra_dsp_bels(cell, row, col, num, cellname):
# Explanation of what comes from and magic numbers. The process is this: you
# create a file with one primitive from the BSRAM family. In my case pROM. You
# give it a completely zero initialization. You generate an image. You specify
# one single unit bit at address 0 in the initialization. You generate an
# one single nonzero bit at address 0 in the initialization. You generate an
# image. You compare. You sweep away garbage like CRC.
# Repeat 16 times.
# The 16th bit did not show much, but it allowed us to discover the meaning of
Expand Down Expand Up @@ -509,6 +509,12 @@ def set_bsram_attrs(db, typ, params):
bsram_attrs['MODE'] = 'ENABLE'
bsram_attrs['GSR'] = 'DISABLE'

# We bring it into line with what is observed in the Gowin images - in the
# ROM, port A has a signal CE = VCC and inversion is turned on on this pin.
# We will provide VCC in nextpnr, and enable the inversion here.
if typ == 'ROM':
bsram_attrs['CEMUX_CEA'] = 'INV'

for parm, val in params.items():
if parm == 'BIT_WIDTH':
val = int(val, 2)
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