Describe the BSRAM regs in GW1NR-9C and GW2AR-18C

Tangnano9k and Tangnano20k have problems with internal registers at the BSRAM output. Here we describe a solution that Gowin uses and which we will repeat in the near future. Signed-off-by: YRabbit <[email protected]>
yrabbit · Jun 24, 2024 · 1c4d4c7 · 1c4d4c7
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diff --git a/doc/bsram-fix.md b/doc/bsram-fix.md
@@ -40,7 +40,16 @@ One more note for the future - if these additional things are intended to correc
 
 ![READ_MODE=1'b0, WRITE_MODE=2'b10](fig/sp-rmode-1-wmode-10.png)
 
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+### Tangnano9k and Tangnano20k
+For chips on these boards, no new elements are formed around the BSRAM, that is, we can conclude that whatever was broken in the previous families was fixed here. However, now the built-in output registers only work with 32 or 36 bits - with a different bit size, the internal registers are disabled (read mode is forced to switch to 1'b0 bypass) and external DFFs are added.
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+Which type is added, DFFCE or DFFRE, is determined by the SYNC parameter.
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+![Tangnano9k and Tangnano20k with READ_MODE=1'b1](fig/sp-rmode-1-9c-20c.png)
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 # TODO
-  - Explore SP in Tangnano9k and Tangnano20k
   - Explore DPB, SDPB and pROM
 
diff --git a/doc/fig/sp-rmode-1-9c-20c.dia b/doc/fig/sp-rmode-1-9c-20c.dia
diff --git a/doc/fig/sp-rmode-1-9c-20c.png b/doc/fig/sp-rmode-1-9c-20c.png