Github: https://github.com/ykqiu/ethernet-udp
This project is a gigabit ethernet in Verilog aimed at FPGA or ASIC where requirements for high-speed data collection is needed. For example, in optical communication, video stream or in high-spped ADC signal capture.
This project is mainly done on Xilinx 7 series (Artix, Kintex) using vivado HLS, but it may also be compatible with other platforms or tools in ASIC/FPGA RTL design.
The idea with this project is to capture the incoming data from high-speed host (PC, etc) and store the high band-width data in DDR3, reducing the complexity and hardware requirement. This project consists of the UDP_RX, UDP_TX and a DDR3 controller.
This module is used to receive high-speed data from ethernet host, and extract the application data from the ethernet frame/packet. The incoming data is in the format of MAC layer protocol, this module will decode whether the packet is IP or APR protocol, then pass the data to appropriate module. If the ethernet packet is an IP packet, then the IP header will be decoded into packet information, such as packet length, IP source and checksum. Assuming that data is sent using the UDP protocol, within the data section of an IPv4 packet, there exists a subset data and header sections. The second word contains the length and checksum of the UDP packet. The packet length is used to determine the number bytes of application data, which will be stored for future use. The main features of UDP_RX are:
- Extract application data from MAC protocol, by stripping the MAC header, IP header and UDP header and send the packet appropriately into memory.
- Calculate CRC, UDP checksum and IP checksum to guarantee the correctness of application data.
- Drop the ethernet frame if any protocol violation happens, including preamble error, SFD error, mac address error, ip address error, checksum error and crc error.
This module is used to send high-speed data out to ethernet device, it is used to encapsulate the application data with various protocol headers. First is the UDP header, then the IP header (at which point it becomes a packet), and then the MAC header. Firstly, The data read from memory is attached with UDP header, that is source port, destination port and pre-calculated udp-checksum. After that, IP header is attached to the front of UDP header, including packet length, IP source, IP destination and IP-checksum, etc. Finally, the mac header and crc are attached to the IP packet, then the packet is sent to ethernet RX through PHY layer. The main features of UDP_TX are:
- Add MAC header, IP header, UDP header and CRC to application data and send the packet appropriately to ethernet device.
- Calculate UDP checksum, IP checksum and CRC to lower the risk of data loss or data error.
This module is a DDR3 controller wrapper of Xilinx MIG 7 DDR3 controller IP, he MIG 7 IP core provides users with two interface options: User Interface (a wrapper over Native interface) and the AXI4 Interface. This project adopt User Interface, which is more cost effective and easier to implement. The module is aimed at storing the application data from ethernet RX or read the data back to ethernet TX. Due to the requirement for high band-width, a high speed memory is needed to match the band-width of ethernet, in this case, 1000 Mbit/s. Therefore, DDR3 is implemented which supports up to 12.8 Gbit/s. In addition to the high band-width, DDR3 also provides huge memory space to store the application data. The MT41J128M16 series DDR3 supports a storage space of 128Meg*16. The DDR3 controller wrapper supports:
- Write command by using app_en, app_wdf_wren, app_addr, app_cmd and app_cmd with appropriate timing.
- Read command by using app_en, app_addr, app_cmd with appropriate timing.
- Controlled data number threshold: send write requests to MIG IP when data number exceeds the threshold, and read requests to when data number is lower than the setting threshold.