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Add niosv #7
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DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/Readme.md
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DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/sample.json
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DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/kernels/simple_dma/src/simple_dma.cpp
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for (unsigned int i = 0; i < (length / 4); | ||
i++) // will be testing with Nios V where an int is 4 bytes | ||
{ | ||
destination[i] = source[i]; | ||
} |
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for (unsigned int i = 0; i < (length / 4); | |
i++) // will be testing with Nios V where an int is 4 bytes | |
{ | |
destination[i] = source[i]; | |
} | |
// will be testing with Nios V where an int is 4 bytes | |
for (unsigned int i = 0; i < (length / 4); i++) { | |
destination[i] = source[i]; | |
} |
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Is this comment meant for the users or to remind the developer to test something?
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for users; to explain why we divide legnth by 4. do you think memcpy
would make more sense here? @jarrodblackburn can you use memcpy
on the Nios® V softcore processor?
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ah understood, then I think it should be rewritten as follows:
for (unsigned int i = 0; i < (length / 4); | |
i++) // will be testing with Nios V where an int is 4 bytes | |
{ | |
destination[i] = source[i]; | |
} | |
// will be testing with Nios V where an int is 4 bytes | |
constexpr kSize = length / 4 | |
for (unsigned int i = 0; i < kSize; i++) { | |
destination[i] = source[i]; | |
} |
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memcpy is present for Nios V but this is the kernel code so not it's applicable here. This change is fine given the DMA is only moving integers. The division was in the original code since I tend to keep everything expressed in bytes (unaligned DMAs get confusing if you deal with a mix of words and bytes).
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it shouldn't be a constexpr anyway because length
is a runtime parameter. I'll write it like this:
void operator()() const {
// This loop does not handle partial accesses (less than 4 bytes) at the
// start and end of the source/destination so ensure they are at least
// 4-byte aligned
for (unsigned int i = 0; i < (length_bytes / 4); i++) {
destination[i] = source[i];
}
}
DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/kernels/simple_dma/src/simple_dma.cpp
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DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/Readme.md
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DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/readme.txt
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...tProgramming/C++SYCL_FPGA/ReferenceDesigns/niosv/software/simple_dma_test/software_build.tcl
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...ogramming/C++SYCL_FPGA/ReferenceDesigns/niosv/software/simple_dma_test/src/simple_dma_test.c
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…ix some spelling in the readme
Adding a New Sample(s) - Nios V
Description
This code sample demonstrates how to use an FPGA IP produced with the Intel® oneAPI DPC++/C++ Compiler with a NIOS V soft CPU in an IP Authoring workflow.
This is the first pass at this code sample.
@yuguen-intel can you please review
@jarrodblackburn can you please review
I'll get Khai Liang to have a look after you, or if you don't have time
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