Extending the solutions to problems in Counter Section

7 - Sequential Logic/2 - Counters/5 - Four-digit Counter.v

@@ -0,0 +1,36 @@
+module top_module (
+    input clk,
+    input reset,   // Synchronous active-high reset
+    output [3:1] ena,
+    output [15:0] q);
+
+    assign ena[1] = (q[3:0] == 9) ? 1 : 0;
+    assign ena[2] = ((q[7:4] == 9) && ena[1]) ? 1 : 0;
+    assign ena[3] = ((q[11:8] == 9) && ena[2]) ? 1 : 0;
+
+    count_bcd c0(clk,reset,1,q[3:0]);
+    count_bcd c1(clk,reset,ena[1],q[7:4]);
+    count_bcd c2(clk,reset,ena[2],q[11:8]);
+    count_bcd c3(clk,reset,ena[3],q[15:12]);
+
+endmodule
+
+module count_bcd (
+    input clk,
+    input reset,        // Synchronous active-high reset
+    input ena,
+    output [3:0] q);
+
+    always@(posedge clk)
+        begin
+            if(reset)
+            	q <= 0;
+            else if (ena)
+            	if(q == 9)
+            		q <= 0;
+           		else
+                q <= q + 1;
+            else
+                q <= q;
+        end    	
+endmodule

7 - Sequential Logic/2 - Counters/6 - Twelve-Hour Clock.v

@@ -0,0 +1,132 @@
+module top_module(
+    input clk,
+    input reset,
+    input ena,
+    output pm,
+    output [7:0] hh,
+    output [7:0] mm,
+    output [7:0] ss); 
+
+    initial pm = 0;
+
+    //counters for seconds
+    count_ss_L c_ss_l(clk,reset,ena,ss[3:0]);
+    count_ss_H c_ss_h(clk,reset,((ss[3:0] == 9) && ena),ss[7:4]);
+
+    //counters for minutes
+    count_ss_L c_mm_l(clk,reset,(ena && (ss[3:0] == 9) && (ss[7:4] == 5)),mm[3:0]);
+    count_ss_H c_mm_h(clk,reset,(ena && (mm[3:0] == 9) && (ss[3:0] == 9) && (ss[7:4] == 5)),mm[7:4]);
+
+    //counters for hours
+    count_hh_L c_hh_l(clk,reset,(ena && (mm[3:0] == 9) && (mm[7:4] == 5) && (ss[7:4] == 5) && (ss[3:0] == 9)),(hh[7:4]==1),pm,pm,hh[3:0]);
+    count_hh_H c_hh_h(clk,reset,(ena && ((hh[3:0] == 9) || ((hh[7:4] == 1) && (hh[3:0] == 2))) && (mm[3:0] == 9) && (mm[7:4] == 5) 
+																																															&& (ss[3:0]==9) && (ss[7:4] == 5)),hh[7:4]);
+
+endmodule
+
+module count_hh_L (
+    input clk,
+    input reset,        // Synchronous active-high reset
+    input ena,
+    input incr_h,
+    input pm_curr,
+    output pm_new,
+    output [3:0] q);
+
+    always@(posedge clk)
+        begin
+            if(reset)
+             	begin
+             		q <= 2;
+                pm_new <= 0;
+             	end
+            else if (ena)
+            	begin
+              	if((q == 1) && incr_h)
+                	begin
+                  	 pm_new <= ~ pm_curr;                        
+                     q <= q + 1;
+                  end
+                 else if((q == 2) && incr_h)
+                 	begin
+                  	q <= 1;
+                    pm_new <= pm_curr;
+                  end
+                 else if(q == 9)
+                 	begin
+  						 			q <= 0;
+                    pm_new <= pm_curr;
+                  end
+           			 else
+                 	begin
+               			q <= q + 1;
+                    pm_new <= pm_curr;
+                  end
+                end
+            else
+            	begin
+              	q <= q;
+               	pm_new <= pm_curr;
+              end
+        	end    	
+endmodule
+
+module count_hh_H (
+    input clk,
+    input reset,        // Synchronous active-high reset
+    input ena,
+    output [3:0] q);
+
+    always@(posedge clk)
+        begin
+            if(reset)
+           	 q <= 1;
+            else if (ena)
+            	if(q == 1)
+              	q <= 0;
+              else
+              	q <= q + 1;
+            else
+           	 q <= q;
+        end    	
+endmodule
+
+module count_ss_L (
+    input clk,
+    input reset,        // Synchronous active-high reset
+    input ena,
+    output [3:0] q);
+
+    always@(posedge clk)
+        begin
+        	if(reset)
+          	q <= 0;
+          else if (ena)
+          	if(q == 9)
+            	q <= 0;
+           	else
+              q <= q + 1;
+          else
+          	q <= q;
+        end    	
+endmodule
+
+module count_ss_H (
+    input clk,
+    input reset,        // Synchronous active-high reset
+    input ena,
+    output [3:0] q);
+
+    always@(posedge clk)
+        begin
+        	if(reset)
+          	q <= 0;
+          	else if (ena)
+            	if(q == 5)
+            		q <= 0;
+           		else
+               	q <= q + 1;
+            else
+            	q <= q;
+        end    	
+endmodule

7 - Sequential Logic/3 - Shift Registers/1 - Four-bit Shift Register.v

@@ -0,0 +1,26 @@
+module top_module(
+    input clk,
+    input areset,  // async active-high reset to zero
+    input load,
+    input ena,
+    input [3:0] data,
+    output reg [3:0] q); 
+
+    always @ (posedge clk or posedge areset)
+        begin
+        	if(areset)
+            	q <= 0;
+    		else if(load)
+                q <= data;
+            else if(ena)
+                begin
+                    q[0] = q[1];
+                    q[1] = q[2];
+                    q[2] = q[3];
+                    q[3] = 0;
+                end
+            else
+                q <= q;
+        end
+endmodule
+

7 - Sequential Logic/3 - Shift Registers/2 - Left-Right Rotator.v

@@ -0,0 +1,28 @@
+module top_module(
+    input clk,
+    input load,
+    input [1:0] ena,
+    input [99:0] data,
+    output reg [99:0] q); 
+
+    integer i;
+    always@(posedge clk)
+        begin
+            if(load)
+                q <= data;
+            else if(ena == 1)
+                begin
+                    for(i = 0; i<100; i=i+1)
+                    		q[i] <= q[(i+1)%100];
+                end
+            else if(ena == 2)
+                begin
+                    for(i = 0; i<100;i=i+1)
+                        q[i] <= q[99 - (100-i)%100];
+                end
+            else
+                q <= q;
+        end
+
+endmodule
+

7 - Sequential Logic/3 - Shift Registers/3 - Left-Right Arithmetic Shift.v

@@ -0,0 +1,28 @@
+module top_module(
+    input clk,
+    input load,
+    input ena,
+    input [1:0] amount,
+    input [63:0] data,
+    output reg [63:0] q); 
+
+    always @ (posedge clk)
+        begin
+            if(load)
+                q <= data;
+            else if(ena)
+                begin
+                    if(amount == 0)
+                        q <= {q[62:0],1'b0};
+                    else if(amount == 1)
+                        q <= {q[55:0],8'b0};
+                    else if(amount == 2)
+                        q <= {{2{q[63]}},q[62:1]};
+            				else
+                        q <= {{9{q[63]}},q[62:8]};
+                end
+            else
+                q <= q;
+        end
+
+endmodule

7 - Sequential Logic/3 - Shift Registers/4 - Five-Bit LFSR.v

@@ -0,0 +1,33 @@
+module top_module(
+    input clk,
+    input reset,    // Active-high synchronous reset to 5'h1
+    output [4:0] q
+); 
+    wire in1,in2,in3,in4,in5;
+
+    assign in1 = reset ? 1'b1 : q[1];
+    assign in2 = reset ? 1'b0 : q[2];
+    assign in3 = reset ? 1'b0 : q[3] ^ q[0];
+    assign in4 = reset ? 1'b0 : q[4];
+    assign in5 = reset ? 1'b0 : q[0] ^ 1'b0;
+
+    d_ff ff1(clk,in1,q[0]);
+    d_ff ff2(clk,in2,q[1]);
+    d_ff ff3(clk,in3,q[2]);
+    d_ff ff4(clk,in4,q[3]);
+    d_ff ff5(clk,in5,q[4]);
+
+endmodule
+
+module d_ff(
+input clk,
+    input d,
+    output q
+);
+    always @ (posedge clk)
+        begin
+            q <= d;
+        end
+endmodule
+
+

7 - Sequential Logic/3 - Shift Registers/5 - Three-Bit LFSR.v

@@ -0,0 +1,22 @@
+module top_module (
+input [2:0] SW,      // R
+input [1:0] KEY,     // L and clk
+output [2:0] LEDR);  // Q
+
+    reg [2:0] LEDR_Next;
+
+    // NOTE: KEY[0] = CLK, KEY[1] = L;
+    always @(*)
+        begin
+            LEDR_Next[0] = KEY[1] ? SW[0] : LEDR[2];
+            LEDR_Next[1] = KEY[1] ? SW[1] : LEDR[0];
+            LEDR_Next[2] = KEY[1] ? SW[2] : LEDR[1] ^ LEDR[2];
+        end
+
+    always @ (posedge KEY[0])
+        begin
+            LEDR <= LEDR_Next;
+        end
+
+endmodule
+

7 - Sequential Logic/3 - Shift Registers/6 - Thirty-Two-Bit LFSR.v

@@ -0,0 +1,28 @@
+module top_module(
+    input clk,
+    input reset,    // Active-high synchronous reset to 32'h1
+    output [31:0] q
+); 
+    reg [31:0] q_next;
+
+    //NOTE: In a primitive shift register, the values are shifted by 1 every clock cycle. We make use of the same property here to define a combinational block feeding the values into the D-FF. The only change occurs in the value of inputs to the D-FF having taps
+
+    always @ (*)
+        begin
+            q_next = q[31:1];
+            q_next[31] = q[0];
+            q_next[21] = q[22] ^ q[0];
+            q_next[1]  = q[2] ^ q[0];
+            q_next[0]  = q[1] ^ q[0];
+        end
+
+    always @ (posedge clk)
+        begin
+            if(reset)
+                q <= 32'b1;
+            else
+                q <= q_next;
+        end
+
+endmodule
+

7 - Sequential Logic/3 - Shift Registers/7 - Shift Register.v

@@ -0,0 +1,21 @@
+module top_module (
+    input clk,
+    input resetn,   // synchronous reset
+    input in,
+    output out);
+
+    reg [3:0] outReg;
+
+    always @ (posedge clk)
+        begin
+        if(~resetn)
+                outReg[3] <= 0;
+            else
+                begin
+                    outReg <= {in,outReg[2:0]};
+                end
+        end 
+    assign out = outReg[0];
+endmodule
+
+

7 - Sequential Logic/3 - Shift Registers/8 - Shift RegisterII.v

@@ -0,0 +1,34 @@
+module top_module (
+    input [3:0] SW,
+    input [3:0] KEY,
+    output [3:0] LEDR
+); //
+
+    // MUXDFF modn(clk,w,r,l,e,qin,qout)
+    MUXDFF mod1(KEY[0], LEDR[1], SW[0], KEY[2], KEY[1], LEDR[0], LEDR[0]);
+    MUXDFF mod2(KEY[0], LEDR[2], SW[1], KEY[2], KEY[1], LEDR[1], LEDR[1]);
+    MUXDFF mod3(KEY[0], LEDR[3], SW[2], KEY[2], KEY[1], LEDR[2], LEDR[2]);
+    MUXDFF mod4(KEY[0], KEY[3], SW[3], KEY[2], KEY[1], LEDR[3], LEDR[3]);
+
+endmodule
+
+module MUXDFF (
+    input clk,
+    input w,
+input r,
+input l,
+input e,
+    input qin,
+output qout);
+
+    wire mux1Out,mux2Out;
+
+    assign mux1Out = e ? w : qin;
+    assign mux2Out = l ? r: mux1Out;
+
+    always @ (posedge clk)
+        qout <=mux2Out;
+
+endmodule
+
+