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[WIP] Bare Metal VCU118 Capability #1892

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43 changes: 43 additions & 0 deletions fpga/src/main/scala/vcu118/Configs.scala
Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,12 @@ class WithSystemModifications extends Config((site, here, up) => {
case SerialTLKey => Nil // remove serialized tl port
})

class WithSystemModificationsBareMetal extends Config((site, here, up) => {
case DTSTimebase => BigInt((1e6).toLong)
case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) // set extmem to DDR size
case SerialTLKey => Nil // remove serialized tl port
})

// DOC include start: AbstractVCU118 and Rocket
class WithVCU118Tweaks extends Config(
// clocking
Expand All @@ -63,6 +69,37 @@ class WithVCU118Tweaks extends Config(
new freechips.rocketchip.subsystem.WithNMemoryChannels(1)
)

class WithVCU118TweaksBareMetal extends Config(
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Can we drop the "BareMetal" naming, and name it UARTTSIVCU118 in all places. The "baremetal" terminology I feel does not accurately describe what the additional capability of these configs is.

//Support for bare metal UART/TSI programs
new WithVCU118UARTTSI ++
new testchipip.tsi.WithUARTTSIClient ++
// clocking
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithMemoryBusFrequency(100) ++
new chipyard.config.WithSystemBusFrequency(100) ++
new chipyard.config.WithControlBusFrequency(100) ++
new chipyard.config.WithPeripheryBusFrequency(100) ++
new chipyard.config.WithControlBusFrequency(100) ++
new WithFPGAFrequency(100) ++ // default 100MHz freq
// harness binders
new WithUART ++
new WithSPISDCard ++
new WithDDRMem ++
// other configuration
new WithDefaultPeripherals ++
new chipyard.config.WithTLBackingMemory ++ // use TL backing memory
new WithSystemModificationsBareMetal ++ // setup busses, setup ext. mem. size
new chipyard.config.WithNoDebug ++ // remove debug module
new freechips.rocketchip.subsystem.WithoutTLMonitors ++
new freechips.rocketchip.subsystem.WithNMemoryChannels(1)
)

class RocketVCU118BareMetalConfig extends Config(
new WithVCU118TweaksBareMetal ++
new chipyard.RocketConfig
)

class RocketVCU118Config extends Config(
new WithVCU118Tweaks ++
new chipyard.RocketConfig
Expand All @@ -75,6 +112,12 @@ class BoomVCU118Config extends Config(
new chipyard.MegaBoomV3Config
)

class BoomVCU118BareMetalConfig extends Config(
new WithFPGAFrequency(50) ++
new WithVCU118TweaksBareMetal ++
new chipyard.MegaBoomConfig
)

class WithFPGAFrequency(fMHz: Double) extends Config(
new chipyard.harness.WithHarnessBinderClockFreqMHz(fMHz) ++
new chipyard.config.WithSystemBusFrequency(fMHz) ++
Expand Down
32 changes: 30 additions & 2 deletions fpga/src/main/scala/vcu118/HarnessBinders.scala
Original file line number Diff line number Diff line change
Expand Up @@ -6,9 +6,12 @@ import chisel3.experimental.{BaseModule}
import org.chipsalliance.diplomacy.nodes.{HeterogeneousBag}
import freechips.rocketchip.tilelink.{TLBundle}

import sifive.blocks.devices.uart.{UARTPortIO}
import sifive.fpgashells.shell._
import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO, UARTParams}
import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}

import freechips.rocketchip.diplomacy.{LazyRawModuleImp}

import chipyard._
import chipyard.harness._
import chipyard.iobinders._
Expand Down Expand Up @@ -37,6 +40,32 @@ class WithDDRMem extends HarnessBinder({
}
})

//Bare Metal Extension
class WithVCU118UARTTSI extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
val rawModule = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[VCU118FPGATestHarness]
val harnessIO = IO(new UARTPortIO(port.io.uartParams)).suggestName("uart_tsi")
harnessIO <> port.io.uart
val packagePinsWithPackageIOs = Seq(
("AW25" , IOPin(harnessIO.rxd)),
("BB21", IOPin(harnessIO.txd)))
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Your comment indicates that this overlaps with the UART device, which uses the UARTOverlay-generated pins in the VCU118TestHarness, but this generates its own pins. Do these overlap with the UARTOverlay pins?

packagePinsWithPackageIOs foreach { case (pin, io) => {
rawModule.xdc.addPackagePin(io, pin)
rawModule.xdc.addIOStandard(io, "LVCMOS18")
rawModule.xdc.addIOB(io)
} }

rawModule.all_leds(0) := port.io.dropped
rawModule.all_leds(1) := port.io.dropped
rawModule.all_leds(2) := port.io.dropped
rawModule.all_leds(3) := port.io.dropped
rawModule.all_leds(4) := port.io.tsi2tl_state(0)
rawModule.all_leds(5) := port.io.tsi2tl_state(1)
rawModule.all_leds(6) := port.io.tsi2tl_state(2)
rawModule.all_leds(7) := port.io.tsi2tl_state(3)
}
})

class WithJTAG extends HarnessBinder({
case (th: VCU118FPGATestHarnessImp, port: JTAGPort, chipId: Int) => {
val jtag_io = th.vcu118Outer.jtagPlacedOverlay.overlayOutput.jtag.getWrappedValue
Expand All @@ -47,6 +76,5 @@ class WithJTAG extends HarnessBinder({
jtag_io.TDO.driven := true.B
// ignore srst_n
jtag_io.srst_n := DontCare

}
})
3 changes: 3 additions & 0 deletions fpga/src/main/scala/vcu118/TestHarness.scala
Original file line number Diff line number Diff line change
Expand Up @@ -84,6 +84,9 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
)))))
ddrNode := TLWidthWidget(dp(ExtTLMem).get.master.beatBytes) := ddrClient

val ledOverlays = dp(LEDOverlayKey).map(_.place(LEDDesignInput()))
val all_leds = ledOverlays.map(_.overlayOutput.led)

/*** JTAG ***/
val jtagPlacedOverlay = dp(JTAGDebugOverlayKey).head.place(JTAGDebugDesignInput())

Expand Down