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Merge pull request #2074 from ucb-bar/dependabot/submodules/toolchain…
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…s/riscv-tools/riscv-isa-sim-824ecdf

Bump toolchains/riscv-tools/riscv-isa-sim from `de5094a` to `824ecdf`
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@abejgonzalez
abejgonzalez authored Oct 8, 2024
2 parents 2b61ac2 + ea059e1 commit dbdf583
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion toolchains/riscv-tools/riscv-isa-sim
Submodule riscv-isa-sim updated 22 files
+2 −2 README.md
+1 −1 configure.ac
+1 −1 disasm/disasm.cc
+6 −6 disasm/isa_parser.cc
+1 −1 fesvr/htif_pthread.h
+0 −1 riscv/csrs.cc
+0 −1 riscv/csrs.h
+2 −2 riscv/debug_module.cc
+1 −1 riscv/decode_macros.h
+2 −1 riscv/execute.cc
+1 −1 riscv/insns/c_ld.h
+1 −1 riscv/insns/c_ldsp.h
+1 −1 riscv/insns/c_sd.h
+1 −1 riscv/insns/c_sdsp.h
+1 −1 riscv/isa_parser.h
+2 −2 riscv/mmu.cc
+4 −3 riscv/mmu.h
+1 −1 riscv/plic.cc
+0 −2 riscv/processor.cc
+1 −1 riscv/v_ext_macros.h
+39 −7 softfloat/f64_to_bf16.c
+2 −3 spike_main/spike.cc

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