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Yosys is included in the latest debian / Ubuntu but not in the older
version used on Travis.
Yosys is a framework for Verilog RTL synthesis. It currently has
extensive Verilog-2005 support and provides a basic set of synthesis
algorithms for various application domains. Selected features and
typical applications:
Verilog / etc.
Yosys can be adapted to perform any synthesis job by combining the
existing passes (algorithms) using synthesis scripts and adding
additional passes as needed by extending the Yosys C++ code base.
Yosys is free software licensed under the ISC license (a GPL compatible
license that is similar in terms to the MIT license or the 2-clause BSD
license).