Upstream Morello EDK-2 Platform changes for FVP #798

vbpandya · 2025-06-09T12:36:50Z

This is an initial PR in upstreaming of Morello Platform.

edk2-platform repository in morello project is hosted at https://git.morello-project.org/morello/edk2-platforms/-/tree/morello/master which is not regularly synced with upstream master and hence have fallen behind. The idea of the effort is to port the extra patches from the above downstream repo to here.

Morello platform code is divided into two parts, the code for FVP and code for actual hardware. This PR is focusing on FVP platform.

I have tested all the patches for build individually and PR as a whole for booting FVP model.
FVP model can be downloaded from https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms/Morello%20Platform%20FVPs

vbpandya · 2025-06-09T12:38:34Z

@jrtc27 it would be great if you could review this PR as well

samimujawar · 2025-07-15T13:56:28Z

@vbpandya your patches have commit-id. Can you drop those and run ./BaseTools/Scripts/PatchCheck.py before using the changes, please?

vbpandya · 2025-07-15T16:07:09Z

@vbpandya your patches have commit-id. Can you drop those and run ./BaseTools/Scripts/PatchCheck.py before using the changes, please?

Done! Thank you for catching it.

Platform/ARM/Morello/Drivers/MorelloNtFwConfigPei/Fvp.c

samimujawar · 2025-07-25T16:12:11Z

Platform/ARM/Morello/MorelloPlatform.dec

+[Ppis]
+  gArmMorelloFvpPlatformInfoDescriptorPpiGuid = { 0x58885983, 0xF46A, 0x437E, { 0xBD, 0xD3, 0x2E, 0x80, 0x3D, 0x58, 0x1E, 0x3E } }
+  gArmMorelloParameterPpiGuid = { 0x8E289A83, 0x44E1, 0x41CF, { 0xA7, 0x41, 0x83, 0x80, 0x89, 0x23, 0x43, 0xA3 } }
+  gArmMorelloSocPlatformInfoDescriptorPpiGuid = { 0xFF5D69AC, 0x6A2A, 0x4E46, { 0xB1, 0x4A, 0xB4, 0x62, 0xB2, 0xCB, 0x2B, 0x4B } }


gArmMorelloSocPlatformInfoDescriptorPpiGuid is not used here. Should this be part of another patch?

Initially I had fdt patch changing everything to use the new fdt lib, but now I melded that patch to where-ever FDT related things are introduced

Looks like you have addressed this. Can you confirm, please?

yes I have removed it

samimujawar · 2025-07-25T16:28:14Z

Platform/ARM/Morello/Drivers/MorelloNtFwConfigPei/Fvp.c

+#include <MorelloPlatform.h>
+#include <libfdt.h>
+
+STATIC EFI_PEI_PPI_DESCRIPTOR  gPpi;


Does this need to be a global variable?
PEIMs cannot have writable global variables.

samimujawar · 2025-08-08T15:47:57Z

Platform/ARM/Morello/MorelloCap.dsc.inc

+[BuildOptions.AARCH64]
+# Required for pre-processing Platform Dxe which includes platform-type specific build flags.
+!ifdef $(ENABLE_MORELLO_CAP)
+  *_CLANGDWARF_AARCH64_CC_FLAGS     = -DENABLE_MORELLO_CAP


Line 13 suggests that ENABLE_MORELLO_CAP is being used in a Platform Dxe.
However, I cannot find -DENABLE_MORELLO_CAP being used anywhere in the code. Is this really needed? if not can we drop it?

Platform/ARM/Morello/Library/PciSegmentLib/PciSegmentLib.c

Platform/ARM/Morello/Library/LcdPlatformLibMorello/Common.c

Platform/ARM/Morello/Drivers/PlatformDxe/PlatformDxeFvp.c

Platform/ARM/Morello/Drivers/MorelloHwConfigPei/MorelloHwConfigPei.c

Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtFvp.asl

LeviYeoReum · 2025-09-02T07:41:38Z

Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h

-          ProximityDomain,                                               \
-          ClockDomain                                                    \
-          ) {                                                            \
+                                                                         CPUInterfaceNumber,                                            \


Could you make a alignment with other item?

Same is for other places

Ahh looks like, uncrustify didn't catch this, pushed new rev with some modification, please let me know if that looks okay

Looks like Uncrustify is not resolving this. Try to make the changes manually and run uncrustify. If that does not fix It we can ignore this issue.

Platform/ARM/Morello/Drivers/MorelloHwConfigPei/MorelloHwConfigPei.c

LeviYeoReum · 2025-09-02T07:54:08Z

Except the @samimujawar's point out, the most of this look good to me.

Thanks!

samimujawar · 2025-12-28T02:16:58Z

...form/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf

-  gArmMorelloTokenSpaceGuid.PcdPciBusMin
-  gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress
-  gArmMorelloTokenSpaceGuid.PcdPciIoBase
+  gArmTokenSpaceGuid.PcdPciBusMax


Please reorder these in alphabetical order.

gArmTokenSpaceGuid.PcdPciBusMin
gArmTokenSpaceGuid.PcdPciIoBase
gArmTokenSpaceGuid.PcdPciIoSize
gArmTokenSpaceGuid.PcdPciMmio32Base
gArmTokenSpaceGuid.PcdPciMmio32Size
gArmTokenSpaceGuid.PcdPciMmio64Base
gArmTokenSpaceGuid.PcdPciMmio64Size

gArmMorelloTokenSpaceGuid.PcdPciIoMaxBase
gArmMorelloTokenSpaceGuid.PcdPciMmio32MaxBase
gArmMorelloTokenSpaceGuid.PcdPciMmio64MaxBase

gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation
gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation

Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.c

Platform/ARM/Morello/Library/PciSegmentLib/PciSegmentLib.c

Platform/ARM/Morello/Library/PlatformLib/PlatformLibFvp.inf

vbpandya · 2025-12-31T13:50:40Z

addressed @samimujawar's latest comments, keeping them open for review

Platform/ARM/Morello/MorelloPlatformFvp.dsc

Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.c

samimujawar · 2026-01-17T02:36:35Z

Platform/ARM/Morello/MorelloCap.dsc.inc

+
+[BuildOptions.AARCH64]
+# Required for pre-processing Platform Dxe which includes platform-type specific build flags.
+!ifdef $(ENABLE_MORELLO_CAP)


Since I don't think tianocore/edk2@a78ec30 is going to be acceptable, do we still need this change?

removed the patch

samimujawar · 2026-01-17T02:57:47Z

...form/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeFvp.inf

-  gArmMorelloTokenSpaceGuid.PcdPciBusMin
-  gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress
-  gArmMorelloTokenSpaceGuid.PcdPciIoBase
+  gArmTokenSpaceGuid.PcdPciBusMax


gArmTokenSpaceGuid.PcdPciBusMin
gArmTokenSpaceGuid.PcdPciIoBase
gArmTokenSpaceGuid.PcdPciIoSize
gArmTokenSpaceGuid.PcdPciMmio32Base
gArmTokenSpaceGuid.PcdPciMmio32Size
gArmTokenSpaceGuid.PcdPciMmio64Base
gArmTokenSpaceGuid.PcdPciMmio64Size

gArmMorelloTokenSpaceGuid.PcdPciIoMaxBase
gArmMorelloTokenSpaceGuid.PcdPciMmio32MaxBase
gArmMorelloTokenSpaceGuid.PcdPciMmio64MaxBase

gEfiMdePkgTokenSpaceGuid.PcdPciIoTranslation
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gEfiMdePkgTokenSpaceGuid.PcdPciMmio32Translation
gEfiMdePkgTokenSpaceGuid.PcdPciMmio64Translation

Format all files with uncrustify Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

PlatformLibMem.c file is going to be different for Morello FVP and Morello SoC platforms since the virtual memory mapping is different so the file PlatformLibMem.c is renamed as PlatformLibMemFvp.c and PlatformLib.inf is renamed as PlatformLibFvp.inf. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

A custom PCI Segment library is required to handle multiple PCIe segments in Morello, as the base PCI Segment library doesn't allow supporting more than a single PCIe segment. This custom platform-specific PCI Segment Library has been adapted from MdePkg/BasePciSegmentLib. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

Morello platform requires a custom platform-specific PCI Express library because the native PCI Express Library only allows for a single ECAM config address to be supplied to it. If there is more than one PCIe root port, it expects the ECAM regions for all the root ports to be contiguous. This is not the case with Morello where the two RPs have their ECAM regions mapped to non-contiguous address ranges and reside in separate PCIe segments. This custom plaform-specific PCI Express library, inherited from MdePkg/BasePciExpressLib, routes the ECAM accesses to the appropriate ECAM region based on the PCIe segment number in the incoming PCIe address. Segment 0 is PCIe root complex and segment 1 is CCIX root complex. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

Set PCDs which are required for enabling PCIe and CCIX. Also move the common inf file from FVP specific dsc to common dsc file. The default value in .dec files are for the SoC and the FVP overrides it. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

Morello has many PcdPcixxx which are defined in gArmTokenSpaceGuid and gEfiMdePkgTokenSpaceGuid, use them instead of creating new PCD. Remove redundant PcdPciBusCount which can be calculated easily. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com> Change-Id: If2bde477266995a4d19fa9b1187dd24af0f7c17b

The FVP module parse the NT_FW_CONFIG device tree and pass the parsed data to other PEI modules via gArmMorelloFvpPlatformInfoDescriptorPpiGuid (on FVP) The same data are passed to the DXE-phase via the gArmMorelloPlatformInfoDescriptorGuid Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

Morello SoC platform support has added and also boot flow modified to reflect the new boot flow for both Morello FVP and Morello SoC platforms Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

Include the module required to enable network stack Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

This change is required to add the support for enabling the persistent storage for SoC alone, and by keeping the emulated storage for FVP, since FVP doesn't have a QSPI controller/flash for enabling the persistent storage. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

Change the AXI Exapansion peripherals size name for Morello FVP Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

Add the SMMU, GIC ITS and Timer memory regions to the MMU translation table. SBSA test running at uefi shell access SMMU, GIC ITS, REFCLK CNTRead, AP_REFCLK CNTCL and AP_REFCLK_NS CNTCTL, which leads to synchronous exception because of the missing MMU translations. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

In DBG2 table, IRQ ID was set as 0 for the UART. This overwrote the IPI0 trigger method to "level", which prevented SGI0 to be enabled again *after* a CPU offline/online cycle. This patch fixes the above issue by assigning the correct IRQ ID for the UART. Also, the frequency has been changed to 24MHz since IOFPGA UART1 is used as the Debug UART. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

Implement LcdHwLib for the ARM Mali Dxx display controller family for use with LcdGraphicsOutputDxe. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

The platform GOP frame-buffer must be within the lower 40-bits of the memory space. To guarantee this and make sure that frame-buffer memory is always available we carve out a reservation at the end of the 32-bit DDR mapping. The size of this carve-out is controlled by the PCD gArmMorelloTokenSpaceGuid.PcdPlatformGopBufferSize and a size of 0 means to disable memory reservation for the platform frame-buffer. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

Because the FVP do not have any input drivers in UEFI we do not want to enable the console redirection on it. However, we want the GOP to be made available to the OS (that may have drivers). This is achieved by setting a mode if one has not already been set. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

The MorelloHwConfigPeim module passes the device tree (HW_CONFIG) from the EL3_FW to the DXE-phase via the gFdtHobGuid HOB. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

On Morello, the EL3 firmware can optionally supply the Device Tree for the hardware (also called HW_CONFIG). If the EL3 firmware provides one, make sure to expose it. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

The Morello platform includes two clusters with CPUs each. Add processor container devices for the two clusters and move the existing processor devices into respective processor containers. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

This patch adds the necessary LPI state and method definitions to support cpuidle when the kernel is booted with ACPI enabled. Co-authored-by: Karl Meakin <karl.meakin@arm.com> Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

vbpandya · 2026-01-20T17:29:34Z

Addressed all the comments..

vbpandya requested a review from samimujawar as a code owner June 9, 2025 12:36

tianocore-assign-reviewers bot assigned vbpandya Jun 9, 2025

vbpandya force-pushed the varshit/3606_morello_fvp_upstream_v2 branch from c92143c to 497ba24 Compare July 15, 2025 16:06

samimujawar reviewed Aug 8, 2025

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LeviYeoReum reviewed Sep 2, 2025

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vbpandya force-pushed the varshit/3606_morello_fvp_upstream_v2 branch from 497ba24 to 067d898 Compare September 5, 2025 15:17

vbpandya mentioned this pull request Sep 25, 2025

Upstream Morello EDK-2 Platform changes for SoC #877

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samimujawar reviewed Dec 28, 2025

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Platform/ARM/Morello/Library/PciSegmentLib/PciSegmentLib.c Outdated Show resolved Hide resolved

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vbpandya mentioned this pull request Dec 29, 2025

Upstream Morello EDK-2 changes tianocore/edk2#11940

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vbpandya force-pushed the varshit/3606_morello_fvp_upstream_v2 branch from 067d898 to 1a8ee14 Compare December 31, 2025 13:49

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samimujawar reviewed Jan 2, 2026

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vbpandya force-pushed the varshit/3606_morello_fvp_upstream_v2 branch from 1a8ee14 to 9d07298 Compare January 8, 2026 12:02

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vbpandya and others added 8 commits January 20, 2026 17:14

Platform/ARM/Morello: Fix formatting

13c08a7

Format all files with uncrustify Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

Platform/ARM/Morello: Update Readme.md

05a3bca

Morello SoC platform support has added and also boot flow modified to reflect the new boot flow for both Morello FVP and Morello SoC platforms Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

patrik-arm and others added 12 commits January 20, 2026 17:14

Platform/ARM/Morello: Enable the network stack for FVP

a3017cf

Include the module required to enable network stack Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

Platform/ARM/Morello/FVP: Change variable name related to AXI

2495a65

Change the AXI Exapansion peripherals size name for Morello FVP Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

Platform/ARM/Morello: Implement LcdHwLib for the ARM Mali Dxx

3183b3d

Implement LcdHwLib for the ARM Mali Dxx display controller family for use with LcdGraphicsOutputDxe. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

Platform/ARM/Morello: Parse HW_CONFIG from EL3_FW

653285c

The MorelloHwConfigPeim module passes the device tree (HW_CONFIG) from the EL3_FW to the DXE-phase via the gFdtHobGuid HOB. Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

Platform/ARM/Morello/FVP: Support cpuidle in ACPI

4496891

This patch adds the necessary LPI state and method definitions to support cpuidle when the kernel is booted with ACPI enabled. Co-authored-by: Karl Meakin <karl.meakin@arm.com> Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>

vbpandya force-pushed the varshit/3606_morello_fvp_upstream_v2 branch from 9d07298 to 4496891 Compare January 20, 2026 17:22

Upstream Morello EDK-2 Platform changes for FVP #798

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Upstream Morello EDK-2 Platform changes for FVP #798

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vbpandya commented Jun 9, 2025

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