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[SOF2.9] backport fixes from Zephyr main #77

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4 changes: 2 additions & 2 deletions drivers/dai/intel/dmic/dmic_nhlt.c
Original file line number Diff line number Diff line change
Expand Up @@ -139,12 +139,12 @@ static int dai_nhlt_get_clock_div(const struct dai_intel_dmic *dmic, const int p

val = dai_dmic_read(dmic, dmic_base[pdm] +
FIR_CHANNEL_REGS_SIZE * dmic->dai_config_params.dai_index + FIR_CONFIG);
LOG_ERR("pdm = %d, FIR_CONFIG = 0x%08X", pdm, val);
LOG_INF("pdm = %d, FIR_CONFIG = 0x%08X", pdm, val);

p_mfir = FIELD_GET(FIR_CONFIG_FIR_DECIMATION, val) + 1;

rate_div = p_clkdiv * p_mcic * p_mfir;
LOG_ERR("dai_index = %d, rate_div = %d, p_clkdiv = %d, p_mcic = %d, p_mfir = %d",
LOG_INF("dai_index = %d, rate_div = %d, p_clkdiv = %d, p_mcic = %d, p_mfir = %d",
dmic->dai_config_params.dai_index, rate_div, p_clkdiv, p_mcic, p_mfir);

if (!rate_div) {
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5 changes: 5 additions & 0 deletions drivers/dma/dma_intel_adsp_hda.c
Original file line number Diff line number Diff line change
Expand Up @@ -326,6 +326,11 @@ int intel_adsp_hda_dma_stop(const struct device *dev, uint32_t channel)

intel_adsp_hda_disable(cfg->base, cfg->regblock_size, channel);

if (!WAIT_FOR(!intel_adsp_hda_is_enabled(cfg->base, cfg->regblock_size, channel), 1000,
k_busy_wait(1))) {
return -EBUSY;
}

return pm_device_runtime_put(dev);
}

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2 changes: 1 addition & 1 deletion soc/xtensa/intel_adsp/ace/power.c
Original file line number Diff line number Diff line change
Expand Up @@ -326,7 +326,7 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
if (state == PM_STATE_SOFT_OFF) {
/* restore clock gating state */
DSPCS.bootctl[cpu].bctl |=
(core_desc[0].bctl & DSPBR_BCTL_WAITIPCG);
(core_desc[cpu].bctl & DSPBR_BCTL_WAITIPCG);

#ifdef CONFIG_ADSP_IMR_CONTEXT_SAVE
if (cpu == 0) {
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