RISC-V 32-bit vector intrinsics kernels #3280
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…dition and reduce to scalar only once per channel
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Me and a group of fellow students have spent the last 12 months developing a set of optimized kernels for RISC-V edge devices running AI applications using 32-bit vector intrinsics as part of our senior undergraduate project.
We developed and tested the kernels using the Spike RISC-V simulator and benchmarked them by running modified versions of the person_detection and micro_speech examples and measuring the resulting cycle counts.
Our new kernels are built under a new build_target called
riscv_vector.Using our kernels, our results for one iteration of
person detectionyielded a 4.1x reduced cycle count compared to the default scalar implementations, and a 2.8x reduction compared to the compiler-vectorized default implementations:Our results for one iteration of
micro speech(including signal functions) yielded a 1.47x reduced cycle count compared to the default scalar implementations, and a 2.5x reduction compared to the compiler-vectorized default implementations:Interestingly we found the auto-vectorization done by the compiler in this instance to increase the cycle count rather than reduce it.
We were unsure if this is something that may be welcomed upstream but decided to make this pull request in case this could be useful for anyone else.