Awesome RISC-V Resources

A curated list of awesome RISC-V resources

Hopefully this repo can serve as a source of inspiration for your RISC-V related projects!

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Contents

• Open Source Implementations
  • Cores
  • SoCs
  • Uncategorized
  • Deprecated
• Open Source Toolchains
  • HDLs
  • Simulators/Emulators
  • Design Environment
  • Verification and Testing Environment
  • Uncategorized
• Technical Resources
  • Books
  • Videos
  • Courses
  • Articles
  • Research Papers and Publications
  • Uncategorized
• Social Media
  • Forums
  • Google Groups
  • Reddit
  • Telegram
• Contribute
• License

Open Source Implementations

A curated list of awesome RISC-V open source implementations which will inspire you to make yours.

Cores

A curated list of RISC-V Cores, available as open source with proper documentations.

• bigPULP
• biRISC-V - biRISC-V - 32-bit dual issue RISC-V CPU
• BOOM - The Berkeley Out-of-Order RISC-V Processor
• CV32E40P - OpenHW Group CORE-V CV32E40P RISC-V IP
• CVA6 - CVA6 RISC-V CPU
• DarkRISCV
• E203 - Hummingbird E203 Opensource Processor Core
• Freedom - by SiFive for its Freedom E300 and U500 platforms
• FWRISC - a Featherweight RISC-V implementation
• FWRISC-S
• Ibex - Ibex RISC-V Core
• KLESSYDRA-F03
• KLESSYDRA-T02 - KLESSYDRA-T02 INTRELEAVED MULTITHREADED PROCESSOR
• KLESSYDRA-T03 - KLESSYDRA-T03 INTRELEAVED MULTITHREADED PROCESSOR
• KLESSYDRA-T13 - KLESSYDRA-T13 INTRELEAVED MULTITHREADED PROCESSOR
• Kronos - Kronos RISC-V
• Leros - a Tiny Processor Core
• lipsi - Lipsi: Probably the Smallest Processor in the World
• Lizard - The Lizard Core
• Maestro
• Minerva - a 32-bit RISC-V soft processor
• MR1
• mriscv
• NEORV32 - The NEORV32 Processor (RISC-V)
• OpenPiton - The world's first open source, general purpose, multithreaded manycore processor
• NutShell
• patmos - a time-predictable VLIW processor
• PicoRV32 - a Size-Optimized RISC-V CPU
• PULP - PULP (Parallel Ultra-Low-Power) is an open-source multi-core computing platform
• Rattlesnake - RISC-V RV32IMC Soft CPU, with a Security-Hardened Processor Core
• Reindeer - PulseRain Reindeer - RISCV RV32I[M] Soft CPU
• ReonV
• RISCV-CLaSH - A RiscV processor implementing the RV32I instruction set written in clash
• riscv-mini
• Riscy - Riscy Processors - Open-Sourced RISC-V Processors
• RiscyOO - RiscyOO: RISC-V Out-of-Order Processors
• Rocket - Rocket Chip Generator 🚀
• RPU - Basic RISC-V CPU implementation in VHDL
• RSD - RSD RISC-V Out-of-Order Superscalar Processor
• RV01
• RV12
• Sail RISC-V - RISCV Sail Model
• SCR1 - SCR1 RISC-V Core
• SERV - SERV is an award-winning bit-serial RISC-V core
• Shakti C-Class - Shakti C-Class Core
• Shakti E-Class - Shakti E-Class Core
• Sodor
• SSRV - SuperScalar-RISCV-CPU
• Starsea
• Steel
• SweRV - EH1 SweRV RISC-V CoreTM 1.8 from Western Digital
• SweRV EH2 - EH2 SweRV RISC-V CoreTM 1.2 from Western Digital
• SweRV EL2 - EL2 SweRV RISC-V CoreTM 1.2 from Western Digital
• Taiga - Taiga is a 32-bit RISC-V processor
• Tiny Risc-V
• VexRiscv
• WARP-V - The open-source RISC-V core IP you can shape to your needs!
• FlexPRET - a 5-stage, fine-grained multithreaded RISC-V* processor

SoCs

A curated list of RISC-V SoCs, available as open sources.

• Icicle - a 32-bit RISC-V system on chip for iCE40 HX8K, iCE40 UP5K and ECP5 FPGAs
• Iob-SoC
• PicoSoC - A simple example SoC using PicoRV32
• Raven - An ASIC implementation of the PicoSoC PicoRV32
• Riscy SoC
• Shakti SoC
• VexRiscv - Briey, and Murax

Uncategorized

• CDL Hardware
• DANA - Dynamically Allocated Neural Network (DANA) Accelerator
• RISCV-FS - RISC-V formal ISA Specification

Deprecated

• Ariane
• SweRV from WD - FPGA Reference Design for the SweRV RISC-V CoreTM from Western Digital
• zscale

Open Source Toolchains

A curated list of open source toolchains which will halp to make your own design.

HDLs

• CHISEL

Simulators/Emulators

A curated list of open source Emulators/Simulators to design and test your RISC-V related work.

• Spike - RISC-V ISA Simulator
• Verilator - The fastest Verilog/SystemVerilog simulator
• Dromajo - Esperanto Technology's RISC-V Reference Model
• TLBSim - Fast TLB simulator for RISC-V systems
• Ripes - a visual computer architecture simulator and assembly code editor
• FireSim - Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation
• FireSim-NVDLA - full-system simulator integrated with NVIDIA Deep Learning Accelerator (NVDLA)
• SweRV ISS
• GAP8 SDK
• Shakti SDK
• FuseSoC - FuseSoC is an award-winning package manager and a set of build tools for HDL
• riscv-VM - OpenHW Group's RISC-V Virtual Machine
• TinyEMU - a system emulator for the RISC-V and x86 architectures
• RARS - RISC-V Assembler and Runtime Simulator

Design Environment

• PULPino - a single-core microcontroller system, based on 32-bit RISC-V cores
• PULPissimo - microcontroller architecture of the more recent PULP chips
• RISC-V LINUX - Build Fedora Gnome Desktop on RISC-V!!
• Treadle - A Chisel/Firrtl Execution Engine
• Chipyard - framework for agile development of Chisel-based systems-on-chip
• Firrtl - Flexible Internal Representation for RTL
• RISC-V GNU Toolchain - RISC-V GNU Compiler Toolchain
• nextpnr - a portable FPGA place and route tool
• LowRISC Chip

Verification and Testing Environment

• RISC-V DV - a SV/UVM based open-source instruction generator for RISC-V processor verification
• RISC-V Tests - unit tests for RISC-V processors
• CHISEL Tester
• RISC-V Torture - RISC-V Torture Test Generator
• RISC-V Formal - RISC-V Formal Verification Framework
• BOOM Attacks - BOOM Speculative Attacks
• Axe - automatic black box testing

Uncategorized

• WebRISC-V - a web-based graphical pipelined datapath simulation environment built for the RISC-V
• BRSIC-V

Technical Resources

Resources to help you make your own designs.

Books

• Digital Design with Chisel or, PDF

Videos

• RISC-V ASM Tutorial Collection - by Western Digital Corporation
• R32V2020 32-Bit RISC CPU Design
• Looking into Hello World on RISC-V by Dennis Clarke
• RISC-V Workshop Zurich

Courses

• VLSI Systems Design - by UC Berkely
• Computer Organization - Fall 2019 - by Boston University
• Computer Architecture, Summer 2017 - by Oakland University
• Organization of Digital Computers Laboratory - by UC Irvine
• Complex Digital Systems - by MIT
• Computer Architecture - Spring 2018 - by Boston University
• Debugging & Verifying Programs - by University of Texas
• Computer Organization II - by Florida State University
• RISC-V ISA using Chisel - by University of Wisconsin–Madison

Articles

• Creating a custom processor with RISC-V
• Making a real processor step by step using RISC-V ISA
• Sail
• RISC-V RV32I assembly with Ripes simulator
• 2019 : A year of RISC-V and Open source silicon
• Research
• RISC-V Offers Simple, Modular ISA
• RISC-V Bases and Extensions Explained
• Learn with Shakti

Research Papers and Publications

• A Case for OS-Friendly Hardware Accelerators
• A Hardware Accelerator for Tracing Garbage Collection
• A Resource-Limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications
• A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI
• A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI
• Accelerating Deep Convolutional Neural Networks Using Specialized Hardware
• AI Requires Many Approaches
• An Agile Approach to Building RISC-V Microprocessors
• An Efficient Instruction Fetch Architecture for a RISC-V Soft Processor on an FPGA
• Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI
• BOOM v2: an open-source out-of-order RISC-V core
• BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox
• Cambricon: An Instruction Set Architecture for Neural Networks
• Chipyard - An Integrated SoC Research and Implementation Environment
• Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs
• Design and Implementation of CNN Custom Processor Based on RISC-V Architecture
• Design and programming of a coprocessor for a RISC-V architecture
• Design of the RISC-V Instruction Set Architecture
• DianNao: A Small-Footprint High-Throughput Acceleratorfor Ubiquitous Machine-Learning
• FPGA-accelerated machine learning inference as a service for particle physics computing
• FirePerf: FPGA-Accelerated Full-System Hardware/Software Performance Profiling and Co-Design
• FireSim: FPGA-Accelerated Cycle-Exact Scale-OutSystem Simulation in the Public Cloud
• GAP-8: A RISC-V SoC for AI at the Edge of the IoT
• Gemmini: An Agile Systolic Array Generator Enabling Systematic Evaluations of Deep-Learning Architectures
• GhostRider: A Hardware-Software System for Memory Trace Oblivious Computation
• GRVI Phalanx: A Massively Parallel RISC-VFPGA Accelerator Accelerator
• Hardware/Software Codesign for Mobile Speech Recognition
• Implementing a TLB Generator with Chisel for RISC-V Architecture
• MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip
• Measuring the Gap between Programmable and Fixed-FunctionAccelerators: A Case Study on Speech Recognition
• Minimizing Computation in Convolutional Neural Networks
• Nested-Parallelism PageRank on RISC-V Vector Multi-Processors
• OSEK-V: Application-Specific RTOS Instantiation in Hardware
• Out of order floating point coprocessor for RISC V ISA
• PHANTOM: Practical Oblivious Computationin a Secure Processor
• Programmable Fine-Grained Power Management and System Analysis of RISC-V Vector Processors in 28-nm FD-SOI
• PULP-NN: Accelerating Quantized Neural Networks on Parallel Ultra-Low-Power RISC-V Processors
• RISC-V out-of-order data conversion co-processor
• RV-CNN: Flexible and Efficient Instruction Set for CNNs Based on RISC-V Processors
• Scratchpad memory: a design alternative for cache on-chip memory in embedded systems
• SHAKTI Processors: An Open-Source Hardware Initiative
• SHAKTI-F: A Fault Tolerant Microprocessor Architecture
• Simty: a Synthesizable General-Purpose SIMTProcessor
• Simty: generalized SIMT execution on RISC-V
• SonicBOOM: The 3rd Generation Berkeley Out-of-OrderMachine
• Specification for the FIRRTL Language
• The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-VProcessor
• The Case for RISC-V in Space
• The RISC-V Instruction Set Manual, Volume I: BaseUser-Level ISA
• The Rocket Chip Generator
• TIMBER-V: Tag-Isolated Memory BringingFine-grained Enclaves to RISC-V
• Towards a High-Performance RISC-V Emulator
• Towards Deep Learning using TensorFlow Lite on RISC-V
• Towards General-Purpose Neural Network Computing
• Tuning Algorithms and Generators for Efficient Edge Inference
• Using FireSim to Enable Agile End-to-End RISC-V ComputerArchitecture Research
• Variable Precision Floating-Point RISC-V Coprocessor Evaluation using Lightweight Software and Compiler Support

Uncategorized

• Linux on RISC-V
• RISC-V
• Intensivate's Learning Journey for Chisel
• CHISEL Bootcamp
• Notes for Rocket-Chip
• Chipyard
• Chisel/FIRRTL Hardware Compiler Framework
• CHISEL Cheatsheet
• FTPVL - FPGA Tool Performance Visualization Library
• RISC-V Notes
• HWPE: A CNN Accelerator for RISC-V
• Tutorial on RISC-V Design and Verification
• Advanced Examples of Using Chisel
• Chisel – Accelerating Hardware Design
• Cookbook
• Methodology for Implementation of Custom Instructions in RISC-V Architecture
• Introduction to Chisel for Biginners
• RISC-V BOOM
• Ripes Wiki
• Open SoC Fabric
• Embedded Linux on RISC-V
• The RISC-V Instruction Set
• How I built a RISC-V CPU Core in a span of 5 days
• UVM

Social Media

These social media profiles will update about recent RISC-V related news.

Forums

• RISC-V official forum
• OSDForum

Google Groups

• RISC-V HW Dev
• RISC-V Teach
• RISC-V ISA Dev
• Chisel Users

Reddit

• RISC-V

Telegram

• RISC-V

Contribute

Contributions are welcome! Please read the contribution guidelines first.

License

To the extent possible under law, Surya Raj has waived all copyright and related or neighboring rights to this work.