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2021.2.0
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@paulmnt paulmnt released this 13 May 05:33
2021.2.0
0bb638f

Added

  • Accelerators

    • Stratus HLS flow
      • MRI-Q: advanced MRI reconstruction algorithm (#112)
      • Cholesky: Cholesky decomposition (#113)
      • Conv2D: 2D convolution with optional pooling (max or avg), bias addition, and ReLU; supported kernel sizes 1x1, 3x3, or 5x5; supported stride 1x1, or 2x2 (#115)
      • GeMM: dense matrix multiplication supporting arbitrary input size and optional ReLU (#115)

  • Accelerator design flows

    • Bump Stratus HLS version to 20.24 (#114)
    • Bump Xcelium version to 19.03 (#114)
    • Require Xcelium to run unit test of accelerators for Stratus HLS (#114)

  • Cache hierarchy

    • Handle RISC-V atomic operations (#114)
    • Preliminary support for Spandex caches [Alsop et al., ISCA'18] (#114)
      (FPGA implementation needs to improve to meet timing)

  • Scratchpad (shared-local memory) tile

  • ASIC Design

    • Template design for ASIC flow (requires access to GF12 technology) (#114)
    • Chip-to-FPGA link that replaces on-chip DDR controllers when not available for the target technology (#114)
    • Digital clock oscillator (DCO) instance (#114)
    • Technology-specific SRAM wrappers (#114)
    • Technology-specific PAD wrappers with configuration pins and orientation selection (#114)
    • Preliminary FPGA proxy design to simulate the chip-to-FPGA link (#114)
    • Single tile, trace-based simulation target to test the chip JTAG debug interface (#114)
    • SDF back-annotation of user-selected IPs (#114)

  • NoC Architecture

    • Increased reserved field of the packet headers from 4 to 8 bits (#114)
      • Support up to 256 interrupt lines
      • Support Spandex extended message types
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