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Ariane 64 #6

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Ariane 64 #6

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5c35635
Update cache extended tags to not use hardcoded values
atcheng2 Apr 8, 2024
e19abb9
Parameterize behavioral SRAM and extended_tag_bits
atcheng2 Jul 22, 2024
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3 changes: 3 additions & 0 deletions common/defs/cache_consts.svh
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Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,9 @@
`define WORD_OFFSET (1 << `BYTE_BITS)
`define LINE_ADDR_BITS (`ADDR_BITS - `SET_RANGE_LO)

`define MIN_SET_BITS 5
`define EXTENDED_TAG_BITS (((`ADDR_BITS-`OFFSET_BITS-`MIN_SET_BITS+8-1)/8)*8)

// Cache sizes
`define BYTES_PER_WORD (1 << `BYTE_BITS)
`define BITS_PER_WORD (`BYTES_PER_WORD << 3)
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6 changes: 3 additions & 3 deletions l2/rtl/l2_localmem.sv
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Expand Up @@ -34,7 +34,7 @@ module l2_localmem (
);

//for following 2 use BRAM data width to aviod warnings, only copy relevant bits to output data
logic [23:0] rd_data_tag_tmp[`L2_NUM_PORTS][`L2_TAG_BRAMS_PER_WAY];
logic [`EXTENDED_TAG_BITS-1:0] rd_data_tag_tmp[`L2_NUM_PORTS][`L2_TAG_BRAMS_PER_WAY];
logic [3:0] rd_data_evict_way_tmp[`L2_EVICT_WAY_BRAMS];
state_t rd_data_state_tmp[`L2_NUM_PORTS][`L2_STATE_BRAMS_PER_WAY];
line_t rd_data_line_tmp[`L2_NUM_PORTS][`L2_LINE_BRAMS_PER_WAY];
Expand All @@ -60,8 +60,8 @@ module l2_localmem (
logic wr_en_line_bank[`L2_LINE_BRAMS_PER_WAY];

//extend to the appropriate BRAM width
logic [23:0] wr_data_tag_extended;
assign wr_data_tag_extended = {{(24-`L2_TAG_BITS){1'b0}}, wr_data_tag};
logic [`EXTENDED_TAG_BITS-1:0] wr_data_tag_extended;
assign wr_data_tag_extended = {{(`EXTENDED_TAG_BITS-`L2_TAG_BITS){1'b0}}, wr_data_tag};
logic [3:0] wr_data_evict_way_extended;
assign wr_data_evict_way_extended = {{(4-`L2_WAY_BITS){1'b0}}, wr_data_evict_way};

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12 changes: 6 additions & 6 deletions l2/rtl/l2_localmem_asic.sv
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Expand Up @@ -33,7 +33,7 @@ module l2_localmem_asic (
output state_t rd_data_state[`L2_NUM_PORTS]
);

logic [23:0] rd_data_mixed_tmp[`L2_NUM_PORTS][`L2_ASIC_SRAMS_PER_WAY];
logic [`ADDR_BITS-8-1:0] rd_data_mixed_tmp[`L2_NUM_PORTS][`L2_ASIC_SRAMS_PER_WAY];
line_t rd_data_line_tmp[`L2_NUM_PORTS][`L2_ASIC_SRAMS_PER_WAY];

//write enable decoder for ways
Expand All @@ -52,14 +52,14 @@ module l2_localmem_asic (
logic wr_en_mixed_bank[`L2_ASIC_SRAMS_PER_WAY];
logic wr_en_line_bank[`L2_ASIC_SRAMS_PER_WAY];

logic [23:0] wr_data_mixed, wr_mixed_mask;
assign wr_data_mixed = {wr_data_hprot, wr_data_state, {(24 - 1 - `STABLE_STATE_BITS - `L2_TAG_BITS){1'b0}}, wr_data_tag};
logic [`EXTENDED_TAG_BITS-1:0] wr_data_mixed, wr_mixed_mask;
assign wr_data_mixed = {wr_data_hprot, wr_data_state, {(`EXTENDED_TAG_BITS-1 - `STABLE_STATE_BITS - `L2_TAG_BITS){1'b0}}, wr_data_tag};

l2_way_t evict_way_arr [`L2_SETS];

//determine mask for writing to shared SRAM
always_comb begin
wr_mixed_mask = 24'b0;
wr_mixed_mask = {`EXTENDED_TAG_BITS{1'b0}};

if (wr_en_put_reqs) begin
wr_mixed_mask[`L2_ASIC_MIXED_SRAM_HPROT_INDEX] = 1'b1;
Expand Down Expand Up @@ -121,7 +121,7 @@ module l2_localmem_asic (
.CE0(rd_en),
.WEM0(wr_mixed_mask));
`else
sram_behav #(.DATA_WIDTH(24), .NUM_WORDS(512)) mixed_sram(
sram_behav #(.DATA_WIDTH(`EXTENDED_TAG_BITS), .NUM_WORDS(512)) mixed_sram(
.clk_i(clk),
.req_i(rd_en),
.we_i(wr_en_port[i] & wr_en_mixed_bank[j]),
Expand All @@ -142,7 +142,7 @@ module l2_localmem_asic (
.CE0(rd_en),
.WEM0(wr_mixed_mask));
`else
sram_behav #(.DATA_WIDTH(24), .NUM_WORDS(512)) mixed_sram(
sram_behav #(.DATA_WIDTH(`EXTENDED_TAG_BITS), .NUM_WORDS(512)) mixed_sram(
.clk_i(clk),
.req_i(rd_en),
.we_i(wr_en_port[i] & wr_en_mixed_bank[j]),
Expand Down
4 changes: 2 additions & 2 deletions llc/rtl/llc_localmem.sv
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Expand Up @@ -76,8 +76,8 @@ module llc_localmem (
//extend to the appropriate BRAM width
logic [3:0] wr_data_state_extended;
assign wr_data_state_extended = {{(4-`LLC_STATE_BITS){1'b0}}, wr_data_state};
logic [23:0] wr_data_tag_extended;
assign wr_data_tag_extended = {{(24-`LLC_TAG_BITS){1'b0}}, wr_data_tag};
logic [`EXTENDED_TAG_BITS-1:0] wr_data_tag_extended;
assign wr_data_tag_extended = {{(`EXTENDED_TAG_BITS-`LLC_TAG_BITS){1'b0}}, wr_data_tag};
logic [3:0] wr_data_evict_way_extended;

always_comb begin
Expand Down
4 changes: 2 additions & 2 deletions llc/rtl/llc_localmem_asic.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -152,7 +152,7 @@ module llc_localmem_asic (
.CE0(rd_en),
.WEM0(wr_mixed_mask));
`else
sram_behav #(.DATA_WIDTH(28), .NUM_WORDS(512)) mixed_sram(
sram_behav #(.DATA_WIDTH(28 + `ADDR_BITS - 32), .NUM_WORDS(512)) mixed_sram(
.clk_i(clk),
.req_i(rd_en),
.we_i(wr_en_port[i] & wr_en_mixed_bank[j]),
Expand All @@ -173,7 +173,7 @@ module llc_localmem_asic (
.CE0(rd_en),
.WEM0(wr_mixed_mask));
`else
sram_behav #(.DATA_WIDTH(28), .NUM_WORDS(512)) mixed_sram(
sram_behav #(.DATA_WIDTH(28 + `ADDR_BITS - 32), .NUM_WORDS(512)) mixed_sram(
.clk_i(clk),
.req_i(rd_en),
.we_i(wr_en_port[i] & wr_en_mixed_bank[j]),
Expand Down