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mcast_mult_src changes #2

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6 changes: 6 additions & 0 deletions core/accelerators/esp_accelerator.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -28,11 +28,15 @@ class esp_accelerator : public sc_module
// DMA read channel
get_initiator<sc_dt::sc_bv<_DMA_WIDTH_> > dma_read_chnl;

get_initiator<sc_dt::sc_bv<1> > dma_write_rsp;

#else

// DMA read channel
cynw_p2p<sc_dt::sc_bv<32> >::in dma_read_chnl;

cynw_p2p<sc_dt::sc_bv<1> >::in dma_write_rsp;

#endif

// Accelerator configuration
Expand Down Expand Up @@ -84,12 +88,14 @@ class esp_accelerator : public sc_module
, dma_read_ctrl("dma_read_ctrl")
, dma_write_ctrl("dma_write_ctrl")
, dma_write_chnl("dma_write_chnl")
, dma_write_rsp("dma_write_rsp")
{
// Clock and reset binding
dma_read_ctrl.clk_rst(clk, rst);
dma_read_chnl.clk_rst(clk, rst);
dma_write_ctrl.clk_rst(clk, rst);
dma_write_chnl.clk_rst(clk, rst);
dma_write_rsp.clk_rst(clk, rst);
}

// Reset functions
Expand Down
2 changes: 2 additions & 0 deletions core/accelerators/esp_accelerator.i.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -26,9 +26,11 @@ inline void esp_accelerator<_DMA_WIDTH_>::reset_dma_write()
#if 0
dma_write_ctrl.reset_put();
dma_write_chnl.reset_put();
dma_write_rsp.reset_get();
#else
dma_write_ctrl.reset();
dma_write_chnl.reset();
dma_write_rsp.reset();
#endif
}

Expand Down
8 changes: 7 additions & 1 deletion core/systems/esp_dma_controller.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -57,11 +57,15 @@ class esp_dma_controller : public sc_module
// DMA read channel (blocking)
b_put_initiator<sc_dt::sc_bv<_DMA_WIDTH_> > dma_read_chnl;

b_put_initiator<sc_dt::sc_bv<1> > dma_write_rsp;

#else

// DMA read channel (blocking)
cynw_p2p<sc_dt::sc_bv<32> >::out dma_read_chnl;


cynw_p2p<sc_dt::sc_bv<1> >::out dma_write_rsp;

#endif

// Accelerator reset
Expand All @@ -77,6 +81,7 @@ class esp_dma_controller : public sc_module
, dma_write_ctrl("dma_write_ctrl")
, dma_write_chnl("dma_write_chnl")
, dma_read_chnl("dma_read_chnl")
, dma_write_rsp("dma_write_rsp")
, acc_done("acc_done")
, acc_rst("acc_rst")
, num_of_write_burst(0)
Expand All @@ -94,6 +99,7 @@ class esp_dma_controller : public sc_module
dma_read_chnl.clk_rst(clk, rst);
dma_write_ctrl.clk_rst(clk, rst);
dma_write_chnl.clk_rst(clk, rst);
dma_write_rsp.clk_rst(clk, rst);
}

// Process
Expand Down
13 changes: 12 additions & 1 deletion core/systems/esp_dma_controller.i.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -14,11 +14,13 @@ void esp_dma_controller<_DMA_WIDTH_, _MEM_SIZE_>::controller()
dma_read_chnl.reset_put();
dma_write_ctrl.reset_get();
dma_write_chnl.reset_get();
dma_write_rsp.reset_put();
#else
dma_read_ctrl.reset();
dma_read_chnl.reset();
dma_write_ctrl.reset();
dma_write_chnl.reset();
dma_write_rsp.reset();
#endif

acc_rst.write(false);
Expand All @@ -33,6 +35,7 @@ void esp_dma_controller<_DMA_WIDTH_, _MEM_SIZE_>::controller()
do { wait(); }
while ( !dma_read_ctrl.nb_can_get()
&& !dma_write_ctrl.nb_can_get()
&& !dma_write_rsp.can_put()
&& !acc_done.read());

// Kernel is done
Expand Down Expand Up @@ -79,7 +82,9 @@ void esp_dma_controller<_DMA_WIDTH_, _MEM_SIZE_>::controller()

// Write request

if (dma_write_ctrl.nb_can_get())
if (dma_write_ctrl.nb_can_get()
&& dma_write_rsp.can_put()
)
{
dma_info_t dma_info;
bool flag = dma_write_ctrl.nb_get(dma_info);
Expand All @@ -94,6 +99,12 @@ void esp_dma_controller<_DMA_WIDTH_, _MEM_SIZE_>::controller()
total_write_bytes += dma_info.length * (_DMA_WIDTH_ / 8);

dma_write(mem_base, burst_size);

bool flag_rsp = dma_write_rsp.put("0");
sc_assert(flag_rsp);

ESP_REPORT_DEBUG("write response repeat = 0");

}
}
}
Expand Down
6 changes: 6 additions & 0 deletions core/systems/esp_system.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,8 @@ class esp_system : public sc_module
// DMA write channel
put_get_channel< sc_dt::sc_bv<_DMA_WIDTH_> > dma_write_chnl;

put_get_channel< sc_dt::sc_bv<1> > dma_write_rsp;

#else

// DMA read control
Expand All @@ -54,6 +56,8 @@ class esp_system : public sc_module
// DMA write channel
cynw_p2p< sc_dt::sc_bv<32> > dma_write_chnl;

cynw_p2p< sc_dt::sc_bv<1> > dma_write_rsp;

#endif

// Internal signals
Expand Down Expand Up @@ -91,6 +95,7 @@ class esp_system : public sc_module
, dma_write_ctrl("dma_write_ctrl")
, dma_read_chnl("dma_read_chnl")
, dma_write_chnl("dma_write_chnl")
, dma_write_rsp("dma_write_rsp")
, conf_info("conf_info")
, conf_done("conf_done")
, acc_rst("acc_rst")
Expand All @@ -110,6 +115,7 @@ class esp_system : public sc_module
dmac->dma_read_chnl(dma_read_chnl);
dmac->dma_write_ctrl(dma_write_ctrl);
dmac->dma_write_chnl(dma_write_chnl);
dmac->dma_write_rsp(dma_write_rsp);
dmac->acc_done(acc_done);
dmac->acc_rst(acc_rst);
}
Expand Down