What is diila?
==============
DIILA is a Device Independent Integrated Logic Analyzer core,
intended for use in FPGA's to log internal signals in the design.
It is written in Verilog HDL.

How to use diila
================
The inputs to diila consists of one 32-bit trigger port
and a data port with configurable width.
The data ports width is configured with the DATA_WIDTH parameter.
Both the trigger port and the data port is logged into internal RAM during
logging.
The core is controlled over a 32-bit wishbone bus interface,
with the following address space (assuming a DATA_WIDTH of 96):

 Write Address 0x0000:          Set trigger and start logging
 Write Address 0x0001:          Set post trigger count (default = 32)
 Write Address 0x0002:          Set trigger skip count (default = 0)

 Read Address  0x0000 - 0x03ff: Read trig trace log
 Read Address  0x0400 - 0x07ff: Read data[95:64] trace log
 Read Address  0x0800 - 0x0bff: Read data[63:32] trace log
 Read Address  0x0C00 - 0x0fff: Read data[31:0] trace log

The most significant bits of the data port are always at the lower
addresses.

As stated above, logging is started by writing the trigger value to
address 0x0000.
After that, data is logged into a circular buffer, until the trigger
condition is met. At this point, logging will continue for the amount
of samples that have been configured in address 0x0001.
Default number of samples is 32.

By writing to address 0x0002, the trigger condition can be skipped for
a certain amount of times. Setting this to 0xffffffff will completely
disable the trigger.

Dumping data and converting to VCD
==================================
In order to use the data, it has to be transferred to a host machine
where it can be interpreted.
Provided is a python script (dump2vcd.py) that accepts dumped data in the form
gdb outputs with the 'x' command:
0x00000000:	0x0000001	0x00000001	0x00000001	0x00000001
0x00000010:	0x0000002	0x00000002	0x00000002	0x00000002

i.e. <address>:\t<data>\t<data>\t<data>\t<data>

and converts it to a Value Change Dump (VCD) file.
The VCD file can be viewed in waveform viewers, such as gtkwave.

When diila is used together with OpenRISC systems, using gdb to
dump the data is probably the most convient way, but other methods
such as printing out the data on an UART would also be possible.

The following sequence of commands will setup a trigger and dump the data
using gdb, where it is assumed that a DATA_WIDTH of 96 is used, the diila cores
wishbone start address is 0x96000000 and the trigger condition is 0x42:
(gdb) set pagination off
(gdb) set *((int*)0x96000000) = 0x42

Perform steps that will cause the trigger to occur.
(gdb) set logging on
(gdb) x/4096

Wait while data is being dumped

(gdb) set logging off

Finally, to convert the dump file into a VCD:

dump2vcd.py gdb.txt > vcdfile.vcd