This core implements a two-dimensional discrete cosine transform accelerator with effective response to a transient based envirronment.
The core is supposed to operate under non standard power level conditions so the computation is expected to halt depending on power availability, hence the name intermittent. After a halt the core is expected to reprise computation from the last saved checkopoint, leaving a transparent interface to the end user.
The effective intermittent properties of this core are only emulated and not hardware synthesizable since current FPGA technology doesn't embedd high speed non volatile memory hardware.
The scope of this core is to demonstrate the use of this framework.
For plug and play usage this dependencies are requeired:
- VSG > 3.1.0
- PYTHON > 3.8.10
- Matplotlip > 3.4.3
- Pillow > 7.0.0
- NumPY > 1.21.2
- GO > 1.16.5
- VIVADO 2020.2
Otherwise the code is fully opensource and can be simulated with any HDL toolchain supporting VHDL 2008.
This code is based on previous work of Michal Krepa on opencores.org licensed under MIT: MDCT
This code is MIT licensed.