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Merge PDLs into Pharo-ArchC #42

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d67d572
Fixed header null brief, file and date (doxygen).
balbertini Jun 29, 2006
1cba1c5
Fixed header null brief, file and date (doxygen).
balbertini Jun 29, 2006
b96aac9
Fixed header null brief, file and date (doxygen).
balbertini Jun 29, 2006
fe6d979
Fixed header null brief, file and date (doxygen).
balbertini Jun 29, 2006
7dbf842
Fixed header null brief, file and date (doxygen).
balbertini Jun 29, 2006
1c6edd7
Fixed models README (Changelog version)
balbertini Jun 29, 2006
6b26c6a
Fixed models README (Changelog version)
balbertini Jun 29, 2006
3466229
Fixed models README (Changelog version)
balbertini Jun 29, 2006
f8b8d39
Updated assembly information for -break- instruction
baldas Jun 30, 2006
68f7b80
Solved the FFT problem: the sparcv8 model instruction behaviors expec…
Jul 10, 2006
02fb889
Added a description of the last bug in the README file (SPARC model)
baldas Jul 11, 2006
42c2c9a
x86(IA32) Archc2.0 porting
valdineyap Jan 10, 2007
9bb7cec
No delay assignements, HI and LO registers created
rjazevedo Apr 18, 2007
1d680e5
Merged mips1-newbingen-branch changes 363:455 into mips1 trunk
baldas Aug 10, 2007
57f0b1f
Merged powerpc-newbingen-branch changes 367:457 into powerpc trunk
baldas Aug 10, 2007
e7c773a
Merged sparcv8-newbingen-branch changes 366:458 into sparcv8 trunk
baldas Aug 10, 2007
f592b1f
updated README file
baldas Sep 6, 2007
a758004
updated README file
baldas Sep 6, 2007
e003341
updated README file
baldas Sep 6, 2007
f514f81
Merged armv5-newbingen-branch:r328:689 into trunk
rafaelauler Jun 2, 2010
d5ad8c2
Added GDB definitions for ARM model
rafaelauler Jun 17, 2010
f707535
PowerPC model bugfix (gdb_funcs lacked compliance with gdb for ArchC …
rafaelauler Aug 6, 2010
c1a7f9d
ACCSIM ok
maxiwell Sep 30, 2010
d3673fc
ACCSIM ok
maxiwell Sep 30, 2010
e093bc9
ACCSIM ok
maxiwell Sep 30, 2010
6152d62
ACCSIM ok
maxiwell Sep 30, 2010
fc39242
newold
maxiwell Sep 30, 2010
5919219
newold
maxiwell Sep 30, 2010
140c589
newold
maxiwell Sep 30, 2010
147c958
newold
maxiwell Sep 30, 2010
a7405b6
accsim
maxiwell Oct 14, 2010
ab7e938
New mips1 version released - 0.7.9
rafaelauler Oct 25, 2010
2d9e2d4
Updating powerpc readme file
rafaelauler Oct 25, 2010
650933c
Updated sparcv8 readme file
rafaelauler Oct 25, 2010
1527b1a
Added readme file for ARM model
rafaelauler Oct 25, 2010
bfe9daf
Reverting changes from 761.
rafaelauler Oct 26, 2010
896dcbc
Reverting back changes from 765 to 764.
rafaelauler Oct 26, 2010
750cc4a
Added compiler generation information.
rafaelauler Feb 4, 2011
25db664
Implementing mips compiler generation
rafaelauler Feb 11, 2011
29e2ef2
bug fix mips compiler model
rafaelauler Feb 18, 2011
f3716df
Updating compiler_info.ac for mips
rafaelauler Feb 22, 2011
3ca52df
Updating compiler_info.ac for mips
rafaelauler Feb 24, 2011
73ab215
mips model compiler info update.
rafaelauler Mar 25, 2011
216b0a6
arm compiler info update
rafaelauler Mar 25, 2011
46ba6c2
Sparc compiler_info update
rafaelauler Mar 25, 2011
0a373ca
Fixed sparcv8 bug when debug model flag is activated.
rafaelauler Mar 28, 2011
0f0d458
Added compiler info for sparcv8 model
rafaelauler Mar 28, 2011
4b6dd54
sparcv8 compiler_info update
rafaelauler Mar 28, 2011
8891f61
Added compiler_info information for powerpc model
rafaelauler Mar 28, 2011
3bec384
Three extra glibc syscalls added for ARM model.
rafaelauler Oct 22, 2011
020d230
New instructions described in the compiler info file.
rafaelauler Feb 15, 2012
e76e78c
ARM model now does not uses global data in favor of multicore capabil…
rafaelauler Apr 11, 2012
7ef49e1
Debug information fixed for LDM.
rafaelauler Apr 20, 2012
5c0f089
Pre 1.0 release - Fix ARM bugs to make the processor work on multiple…
bcardosolopes May 25, 2012
6e716fd
Pre 1.0 release - Rename mips files
bcardosolopes May 25, 2012
cd00135
Pre 1.0 release - Rename sparc files
bcardosolopes May 25, 2012
f46d042
Pre 1.0 release - Change some parameters to enable multiprocessor work
bcardosolopes May 25, 2012
d80fc19
Fixing ARM model cast bugs.
May 2, 2013
7495965
Forgot to comment DEBUG directive in ARM model.
May 2, 2013
1cb95e5
Fixing another ARM model bug.
May 2, 2013
a583930
Rolling back a small change in arm_syscall to avoid glibc loadings to…
May 2, 2013
ce6d163
Turning off sparc model debug flag.
May 8, 2013
8cf5e28
Substitute 'mips1' for just 'mips'
rjazevedo Mar 5, 2014
9ee95cb
Handle the stack correctly in multicore systems
rjazevedo Mar 5, 2014
cf422ab
Fixing bugs in BX, RSC and SBC instructions.
maxiwell Jul 30, 2014
345a25e
Fixing bugs in DEBUG mode
maxiwell Jul 30, 2014
b2e3963
Updating the syscalls to work with new libac_sysc. IMPORTANT: Use the…
maxiwell Jul 30, 2014
eb95813
Updating README file
maxiwell Jul 30, 2014
ef9ea6b
Adding PowerSC-based header file and power estimation tables based on…
Oct 8, 2014
f874a53
Adding PowerSC-based header file and power estimation tables based on…
Oct 8, 2014
78bfd86
PowerSC: Move all 'csv' files into 'powersc' dir
maxiwell Oct 9, 2014
b67170a
Moved all 'csv' files into 'powersc' dir
maxiwell Oct 9, 2014
d4f1c90
PowerSC: using 'readlink /proc/self/exe' to get the model path to fin…
maxiwell Oct 9, 2014
d9cfe6c
PowerSC: using 'readlink /proc/self/exe' to get the model path to fin…
maxiwell Oct 9, 2014
5200710
PowerSC: the csv tables path by Define on Makefile (-DPOWER_SIM=/powe…
maxiwell Oct 9, 2014
24447ef
PowerSC: the csv tables path by Define on Makefile ( -DPOWER_SIM=$(PW…
maxiwell Oct 9, 2014
ec11a82
Adding "ac_reg id" at the processor model. We will use this register …
Oct 29, 2014
60a2db7
Adding "ac_reg id" at the processor model. This register will the use…
Oct 29, 2014
a72f81f
Adding "ac_reg id" at the processor model. This register will be used…
Oct 29, 2014
be44468
Adding "ac_reg id" at the processor model. This register will be used…
Oct 29, 2014
f1b7de4
Adding new Power tables for mips.
lianaduenha Nov 10, 2014
8e60de2
Adding new power tables for SPARC.
lianaduenha Nov 10, 2014
56287e4
[Memory] Set 512MB in arm.ac as default
maxiwell Dec 8, 2014
10b289b
[Memory] Set 512MB in powerpc.ac as default
maxiwell Dec 8, 2014
68ef2d5
[Regbank] Fixed the number of registers in 16. The model had wrongly …
maxiwell Dec 15, 2014
22011e1
[LSM/STM Instr] Special case in LSM/STM was handled. Now, it's possib…
maxiwell Jan 2, 2015
4a508c9
[FIX] I removed the test of ac_wait_sig from the sparc_isa.cpp file,…
lianaduenha Jan 20, 2015
fb01aca
Update byte and half word instructions to operate on word load and st…
rjazevedo Apr 2, 2015
2355798
Removing extra commented lines in the code
rjazevedo Apr 2, 2015
f846e9f
Update byte and half word instructions to operate on word load and st…
rjazevedo Apr 2, 2015
e98ecf4
Merge branch 'master' of https://github.com/archc/mips
rjazevedo Apr 6, 2015
a55c7f0
adding debug version
rjazevedo Apr 6, 2015
686c277
Updating memory access instructions to only use word methods for read…
rjazevedo Apr 7, 2015
910e743
New description files following Github Markup
tiagofalcao Apr 28, 2015
f11370b
New description files following Github Markup
tiagofalcao Apr 28, 2015
25cb48d
New description files following Github Markup
tiagofalcao Apr 27, 2015
1a8fdbe
New description files following Github Markup
tiagofalcao Apr 28, 2015
29f1233
Removing NOP instruction from MIPS. MIPS does not have a NOP instruction
rjazevedo May 4, 2015
97975dd
PowerSC with new tables and new header (from MPSoCBench)
maxiwell Oct 7, 2015
3511a40
PowerSC with new tables (from MPSoCBench)
maxiwell Oct 7, 2015
869a736
Added two .ac files to use with MPSoCBench.
maxiwell Oct 7, 2015
ffc0800
mips_isa.ac with set_cycles annotation per instruction
maxiwell Oct 7, 2015
de588c6
powerpc_isa.ac with set_cycles annotation per instruction
maxiwell Oct 7, 2015
4b5fb42
Added two .ac files to use with MPSoCBench.
maxiwell Oct 7, 2015
18be8f9
Behaviors code using a generic way to data request
maxiwell Oct 7, 2015
fcf7ece
Behaviors code using a generic way to data request
maxiwell Oct 7, 2015
9fd2d2d
PowerSC with new tables and new header (from MPSoCBench)
maxiwell Oct 7, 2015
e161474
sparc_isa.ac with set_cycles annotation per instruction
maxiwell Oct 7, 2015
b52eac0
Behaviors code using a generic way to data request
maxiwell Oct 7, 2015
bb44096
Added two .ac files to use with MPSoCBench.
maxiwell Oct 7, 2015
ca23935
Added two .ac files to use with MPSoCBench.
maxiwell Oct 7, 2015
336ebc5
arm_isa.ac with set_cycles annotation per instruction
maxiwell Oct 7, 2015
55c3f41
Interrupt handler inactive in standalone configuration
maxiwell Oct 7, 2015
2553096
Changing Makefile.archc to Makefile in README.md
maxiwell Oct 7, 2015
3f2b869
Changing Makefile.archc to Makefile in README.md
maxiwell Oct 7, 2015
738fcf9
Changing Makefile.archc to Makefile in README.md
maxiwell Oct 7, 2015
c6910c1
Changing Makefile.archc to Makefile in README.md
maxiwell Oct 7, 2015
0424264
Disabling Interrupt handler using macros in model_isa.cpp.
maxiwell Oct 7, 2015
a73d930
Disabling Interrupt handler using macros in model_isa.cpp.
maxiwell Oct 7, 2015
1dbbb81
Disabling Interrupt handler using macros in model_isa.cpp.
maxiwell Oct 7, 2015
5ae07cd
Update .gitignore with intr_handlers files
maxiwell Oct 7, 2015
d771105
Update .gitignore with intr_handlers files
maxiwell Oct 7, 2015
7a5944e
Update .gitignore with intr_handlers files
maxiwell Oct 7, 2015
e68c831
Update .gitignore with intr_handlers files
maxiwell Oct 7, 2015
b4958b8
Update .gitignore with intr_handlers files
maxiwell Oct 7, 2015
d204741
Update .gitignore with intr_handlers files
maxiwell Oct 7, 2015
3f7276b
Ignoring intr_hanlders.cpp and template files
maxiwell Oct 8, 2015
532ade4
Ignoring intr_hanlders.cpp and template files
maxiwell Oct 8, 2015
5cb66e2
Ignoring intr_hanlders.cpp and template files
maxiwell Oct 8, 2015
bead144
Ignoring intr_hanlders.cpp and template files
maxiwell Oct 8, 2015
ecc5e07
BUGFIX: find PowerSC tables correctly inside arch_power_stats.H
maxiwell Oct 14, 2015
f80b438
BUGFIX: find PowerSC tables correctly inside arch_power_stats.H
maxiwell Oct 14, 2015
2eb30a5
Behaviors code using a generic way to data request
maxiwell Oct 16, 2015
3dfe79e
DFS support to sparc model
maxiwell Oct 16, 2015
ec75ede
Update HISTORY.md with changes in the version 2.4
maxiwell Oct 16, 2015
b18f240
Update HISTORY.md with changes in the version 2.4
maxiwell Oct 16, 2015
2eb3444
Update HISTORY.md with changes in the version 2.4
maxiwell Oct 16, 2015
784c091
Update HISTORY.md with changes in the version 2.4
maxiwell Oct 16, 2015
8088dd4
Added the tw and twi instructions
shingarov Jan 24, 2016
7e47a7d
Added various forms of the TRAP instruction
shingarov Jan 24, 2016
2aadb71
Implementing get_buffer_addr to comply with new syscall interface
rafaelauler Feb 29, 2016
521a808
Implementing is_mmap_anonymous to comply with new syscall interface
rafaelauler Mar 1, 2016
f6185fa
Implementing host2guest/guest2host to comply with new syscall interface
rafaelauler Mar 4, 2016
ebe3725
Add slot for clock_gettime in syscall vector
rafaelauler Mar 4, 2016
4757b1b
Merge pull request #1 from rafaelauler/master
maxiwell Mar 7, 2016
3e1f489
[GDB] Fixing the read/write mem (gdb_funcs) with the INST_PORT
maxiwell Mar 17, 2016
74491cf
GDB machine descriptor
shingarov Mar 26, 2016
13ee14b
GDB machine descriptor
shingarov Mar 26, 2016
bf480c7
Do not fix l=0 in cmp.set_decoder
shingarov Apr 10, 2016
14b0b12
Update sparc_nonblock.ac
lianaduenha Jun 30, 2016
e5e3a6f
Adding an interrupt port at the sparc_nonblock.ac file
lianaduenha Jun 30, 2016
fd37d4c
[.gitignore] Adding the syscall.cpp.tmpl
maxiwell Jul 1, 2016
becb273
[.gitignore] Adding the syscall.cpp.tmpl
maxiwell Jul 1, 2016
c813ffa
[.gitignore] Adding the syscall.cpp.tmpl
maxiwell Jul 1, 2016
603c175
Explicit ignore expression result
tiagofalcao Jul 3, 2016
76f6698
end of non-void function: bypass_read
tiagofalcao Jul 3, 2016
03f375a
Less than 0 is always false with unsigned values
tiagofalcao Jul 3, 2016
fefcb41
first commit
rafaelauler Jul 5, 2016
fc90a60
[NFC] [isa.cpp] Removing global support functions
maxiwell Jul 7, 2016
d13835f
[NFC] Fixing lowest level reference in arm_isa.cpp
maxiwell Jul 8, 2016
f6d1395
Fixing Load Reg Halfword instruction (LDRH)
maxiwell Jul 12, 2016
97810e8
Fixing Load Reg Signed Halfword instr (LDRSH)
maxiwell Jul 13, 2016
cb0181c
Removing 0xFFFF mask from LDRH and LDRSH instr
maxiwell Jul 13, 2016
0194b7e
[NFCI] Fixing lowest level reference in arm_isa.cpp
maxiwell Aug 5, 2016
2b17291
Removing the 'ref' from arm_isa.cpp
maxiwell Aug 6, 2016
d334233
Necessary model files
Pavani14 Jul 6, 2016
2d36624
[NFC] Formatted according to clang-format
Pavani14 Jul 8, 2016
60207a4
[NFC] Formatted according to clang-format
Pavani14 Jul 8, 2016
b15e1c9
[NFC] Formatted according to clang-format
Pavani14 Jul 8, 2016
07673cd
[NFC] Formatted according to clang-format
Pavani14 Jul 8, 2016
1cd8075
[gdb] Fixing data access in gdb functions
maxiwell Aug 12, 2016
bbd7baa
[gdb] Fixing data access in gdb functions
maxiwell Aug 12, 2016
40581f5
Redefined load, branch, store, shift instructions
Pavani14 Jul 25, 2016
7c900e2
[SB_Type & UJ_Type] SB_Type and UJ_Type instruction encoding added
Pavani14 Jul 25, 2016
6640760
Atomic instructions added
Pavani14 Aug 12, 2016
305abbc
LR.W and SC.W added
Pavani14 Aug 12, 2016
4a845ec
Added floating point register bank
Pavani14 Aug 13, 2016
45999c9
Added instructions FSW and FLW
Pavani14 Aug 13, 2016
c7c5c10
Added FP Computational Instructions
Pavani14 Aug 18, 2016
6c5d6c0
[NFC] Added sign_extension in riscv_isa_helper.H
Pavani14 Aug 18, 2016
ecf4c34
[NFC] Removed unneccessary bit shifting in SLL, SRA
Pavani14 Aug 18, 2016
7bd63c0
[FLD & FSD] Added load and store instr for Double-precision
Pavani14 Aug 18, 2016
3d83606
Merge pull request #2 from Pavani14/RV32IM
rafaelauler Aug 19, 2016
6a96308
[gdb] Add gdb definitions and fix gdb functionality
rafaelauler Aug 22, 2016
1ec1d2d
[gdb] Fix number of registers
rafaelauler Aug 22, 2016
af01a19
[syscalls] Fix register where argv pointers are stored
rafaelauler Aug 22, 2016
13c9818
Testing functions for RISC-V model
Pavani14 Aug 19, 2016
6164d3c
File to ignore ~ files
Pavani14 Aug 19, 2016
fd0ca3a
Added Double-FP computation Instructions
Pavani14 Aug 22, 2016
b3f055c
Added FP and Double-FP conversion instructions
Pavani14 Aug 22, 2016
fbee603
Added FP move instructions
Pavani14 Aug 22, 2016
c6b22e3
[FMV.D] Added Double-FP move instruction
Pavani14 Aug 22, 2016
ed24e8a
[FEQ.S FLT.S FLE.S]Added FP compare instructions
Pavani14 Aug 20, 2016
124a45c
[FEQ.D FLE.D FLT.D]Added Double-FP comparison instructions
Pavani14 Aug 22, 2016
a7a4c0b
Mibench automotive programs & Makefiles
Pavani14 Aug 20, 2016
2f82faa
Platform for creating elf
Pavani14 Aug 20, 2016
37e8fd8
README explaining the functioning of the model
Pavani14 Aug 20, 2016
0e456d0
[FMV.S] Added FP move instruction
Pavani14 Aug 21, 2016
60bcaad
Necessary files for creating executables
Pavani14 Aug 21, 2016
1657e0d
Programs for testing FP instructions
Pavani14 Aug 21, 2016
fb36feb
Added custom isnan function for Double-FP
Pavani14 Aug 22, 2016
e03be26
[NFC] Removed math.h
Pavani14 Aug 22, 2016
bf6d332
[FLD FSD] Changed definitions of FLD & FSD
Pavani14 Aug 22, 2016
03a79b1
[NFC] Added comments to increase readability
Pavani14 Aug 22, 2016
4265875
Merge pull request #3 from Pavani14/RV32IM
rafaelauler Aug 23, 2016
1da6bff
Fix formatting, improve comments and README [NFC]
rafaelauler Aug 23, 2016
603a5f9
Mention future work on GDB at the README file [NFC]
rafaelauler Aug 23, 2016
2e39be2
Fix formatting in README to display correctly at github [NFC]
rafaelauler Aug 23, 2016
189b927
Some bogus compiler_info, just to get Petrich parser to shut up
shingarov Oct 10, 2018
1cfca22
Temporary hack around unimplemented syntax for alternate in Type_FT
shingarov Oct 10, 2018
b1c6859
Empty compiler_info
shingarov Oct 10, 2018
92d8f75
Added the GDB XML machine descriptors back as the Pharo version has RSP
shingarov Jul 20, 2019
073b0a6
Added the GDB XML machine descriptors back as the Pharo version has RSP
shingarov Jul 20, 2019
58d8686
Fix trapcond mnemonic name
shingarov Jun 9, 2020
b0207eb
Some IA32.xml
shingarov Jun 26, 2020
38c5b25
Add *.swp to gitignore
shingarov Jun 26, 2020
0a66e4c
Concrete syntax for mov pc, lr
shingarov Jun 29, 2020
5967deb
Add some minimal MSR syntax, barely enough for Cog
shingarov Sep 17, 2020
199d36d
ba, bla are not PC-relative
shingarov Oct 2, 2020
b7ca43d
Change %imm to %exp for offset (lwz, stw)
shingarov Oct 2, 2020
0bf25fd
Add extended form for sc
shingarov Oct 2, 2020
0d86fb5
Fix DSP breaking Cog
shingarov Nov 18, 2020
aea73b3
Add mtxer extended mnemonic
shingarov Nov 18, 2020
df8f9a9
Add nop extended mnemonic for or 0,0,0
shingarov Nov 18, 2020
9847248
Add `merge-pdls.sh` script to merge individual architecures
janvrany Oct 25, 2021
996b300
Merge individual architectures into a single repository
janvrany Oct 25, 2021
f72202c
Remove `merge-pdls.sh` script as it's no longer needed
janvrany Oct 25, 2021
8e4d3b7
RISC-V: complete revamp of RV64 PDL
janvrany Oct 25, 2021
c35f4b9
RISC-V: add notice to `riscv64_isa.ac`
janvrany Jul 1, 2022
e55ddcb
RISC-V: enable F and D extensions
janvrany Jul 1, 2022
dbe8f88
RISC-V enable A extension
janvrany Jul 2, 2022
8a96081
Merge pull request #1 from janvrany/pr/riscv-support-F-D-and-A-extens…
janvrany Jul 9, 2022
ce043b6
Add generic assembly syntax for `tw` and `twi` instructions
janvrany Sep 6, 2022
45dd293
Add 64-bit traps on POWER
shingarov Sep 7, 2022
085988a
Fix MIPS integer register conventions
shingarov Sep 11, 2022
689607d
MIPS: Specify enough operands to syscall
shingarov Sep 11, 2022
221ec3e
POWER: add PowerPC64 architecture
janvrany Nov 14, 2022
3320086
POWER: revert "Add 64-bit traps on POWER"
janvrany Nov 14, 2022
f8f9f3c
POWER: add `ld`, `ldu`, `ldx`, `ldux`, `std`, `stdu`, `stdx` and `stdux`
janvrany Nov 16, 2022
5bea6a6
POWER: add `extsw`
janvrany Nov 17, 2022
bb845b7
POWER: model `bc`, `bca`, `bcl` and `bcla` as single instruction
janvrany Nov 23, 2022
0eb1f6f
POWER: add branch mnemonics incorporating conditions
janvrany Nov 23, 2022
2d466ed
Merge pull request #5 from janvrany/pr/powerpc64-support
shingarov Nov 25, 2022
0085071
Add the original ArchC reference manuals
shingarov May 4, 2023
512ac22
Add PowerPC isync (POWER: ics) instruction
shingarov May 18, 2024
f7faa16
Add PowerPC sync (POWER: dcs) instruction
shingarov May 18, 2024
39b1325
Add PowerPC mfmsr, mtmsr
shingarov May 23, 2024
e3252ef
Merge PDLs
janvrany Aug 5, 2024
8537cc3
Remove support for specifying PDL directory
janvrany Aug 6, 2024
8d801e0
Update makefiles and README after merging in PDLs
janvrany Aug 6, 2024
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1 change: 0 additions & 1 deletion .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,6 @@
GNUmakefile.local

# Build by-products
pdl
MachineArithmetic

# Smalltalk/X
Expand Down
3 changes: 3 additions & 0 deletions .gitmodules
Original file line number Diff line number Diff line change
@@ -1,3 +1,6 @@
[submodule "makefiles"]
path = makefiles
url = https://github.com/janvrany/smalltalk-makefiles.git
[submodule "pdl/riscv/riscv-opcodes"]
path = pdl/riscv/riscv-opcodes
url = https://github.com/riscv/riscv-opcodes.git
17 changes: 4 additions & 13 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -27,19 +27,10 @@ Either use shortcut:
1. Clone the repository

```
git clone https://github.com/shingarov/Pharo-ArchC ArchC
```

2. Get PDLs:

```
cd ArchC
./get-pdls.sh
git clone --recurse-submodules https://github.com/shingarov/Pharo-ArchC ArchC
```

Alternatively, you may symlink `pdl` directory wherever you keep your PDLs

3. Download Pharo
2. Download Pharo

```
mkdir ArchC/pharo
Expand All @@ -49,7 +40,7 @@ Either use shortcut:
curl https://get.pharo.org/64/80+vm | bash
```

4. Load code into Pharo image:
3. Load code into Pharo image:

```
./pharo Pharo.image save archc
Expand All @@ -67,7 +58,7 @@ Either use shortcut:
2. Clone the repository:

````
git clone https://github.com/shingarov/Pharo-ArchC.git.git
git clone --recurse-submodules https://github.com/shingarov/Pharo-ArchC.git.git
````

3. In Smalltalk/X, execute:
Expand Down
15 changes: 0 additions & 15 deletions get-pdls.sh

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24 changes: 24 additions & 0 deletions pdl/arm/.gitignore
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Makefile
Makefile.archc
arm.H
arm.cpp
*.o
*.x
*.a
arm_arch.H
arm_arch.cpp
arm_arch_ref.H
arm_arch_ref.cpp
arm_bhv_macros.H
arm_isa.H
arm_isa.cpp.tmpl
arm_isa_init.cpp
arm_parms.H
arm_syscall.H.tmpl
arm_syscall.cpp.tmpl
main.cpp
main.cpp.tmpl
arm_ih_bhv_macros.H
arm_intr_handlers.H
arm_intr_handlers.cpp*
12 changes: 12 additions & 0 deletions pdl/arm/CONTRIBUTING.md
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# Contributing

## Submitting a Pull Request

1. Fork it.
2. Create a branch (`git checkout -b my_project`)
3. Commit your changes (`git commit -a`) [Tips for better commit message](https://robots.thoughtbot.com/5-useful-tips-for-a-better-commit-message)
4. Push to the branch (`git push origin my_project`)
5. Open a [Pull Request][1]
6. Enjoy a refreshing Diet Coke and wait doing more

[1]: https://github.com/ArchC/arm/pulls
74 changes: 74 additions & 0 deletions pdl/arm/COPYING
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ArchC DEVELOPMENT PUBLIC LICENSE

Everyone is permitted to copy and distribute verbatim copies of this
license document, but changing it is not allowed.

Preamble

You received this software from a trusted source and for research
purposes. Using or modifying this Program implies full acceptance of
this license. Please contact the person who send or gave you access to
this program for further information.

ArchC DEVELOPMENT PUBLIC LICENSE
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION


This license extends to all Programs contained in the package that
you received, including all subdirectories from this root, except if
the file header indicates another license.

Activities other than copying, distribution and modification are not
covered by this License; they are outside its scope.

1. You may copy verbatim copies of the Program's source code as you
receive it, in any medium, for personal use, provided that you copy
copyright notice and disclaimer of warranty; and keep intact all the
notices that refer to this License and to the absence of any warranty.

Personal use can be extended to a laboratory facility or a shared room
only if you are in charge of a research group that contributes to this
program and only with developing and research purposes.

2. You may modify your copy or copies of the Program or any portion
of it, thus forming a work based on the Program, and copy such
modifications or work under the terms of Section 1 above, provided
that you also meet all of these conditions:

a) You must cause the modified files to carry prominent notices
stating that you changed the files and the date of any change.

b) You must not share, publish or distribute this program, either
in parts or in original form. You must not share, publish or
distribute programs that use this Program, either in parts or in
its original form.


3. You are not required to accept this License, since you have not
signed it. However, nothing else grants you permission to modify or
distribute the Program or its derivative works. These actions are
prohibited by law if you do not accept this License. Therefore, by
modifying or using the Program (or any work based on the Program), you
indicate your acceptance of this License to do so, and all its terms
and conditions for copying, distributing or modifying the Program or
works based on it.

It is not the purpose of this section to induce you to infringe any
patents or other property right claims or to contest validity of any
such claims; this section has the sole purpose of protecting the
integrity of the software in its development phase.

NO WARRANTY

4. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
REPAIR OR CORRECTION.

END OF TERMS AND CONDITIONS

36 changes: 36 additions & 0 deletions pdl/arm/HISTORY.md
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## 2.4.0

* Revision numbers following the ArchC release
* Instructions with cycles annotations
* Two new .ac files to use with MPSoCBench (block and nonblock)
* arm_isa.cpp using the reserved work DATA_PORT to data request. See the [commit message](https://github.com/ArchC/arm/commit/2eb30a551d11636adaede7db86167b43269d56e8).
* Interrupt handler support. It is inactive in standalone simulator.

[Full changelog](https://github.com/ArchC/arm/compare/v2.3.0...v2.4.0)

## 2.3.0
* Revision numbers following the ArchC release
+ Added id register for core identification
* Special case in LSM/STM was handled. Now, it's possible use Rn in Rlist, e.g., 'push {sp, ...}'
* Fixed the number of register in 16

[Full changelog](https://github.com/ArchC/arm/compare/v1.0.1...v2.3.0)

## 1.0.1
* Bugfix in BX, RSC and SBC instructions

[Full changelog](https://github.com/ArchC/arm/compare/v1.0.0...v1.0.1)

## 1.0.0
* ArchC 2.2 compliant

[Full changelog](https://github.com/ArchC/arm/compare/v0.7.0...v1.0.0)

## 0.7.0

* Model passed selected Mediabench and Mibench applications
* ArchC 2.1 compliant
* Support for automatic generation of binary tools
* Support for dynamic linker and loader when reading ELF files
* Support for GDB
* Support for compiled simulator and interpreted simulator
75 changes: 75 additions & 0 deletions pdl/arm/README.md
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ARMv5e ArchC functional model
=====

This is the ARMv5e ArchC functional model.

License
-------
- ArchC models are provided under the ArchC license.
See [Copying](COPYING) file for details on this license.

acsim
-----
This model has the system call emulation functions implemented,
so it is a good idea to turn on the ABI option.

To use acsim, the interpreted simulator:

acsim armv5e.ac -abi (create the simulator)
make (compile)
armv5e.x --load=<file-path> [args] (run an application)

The [args] are optional arguments for the application.

There are two formats recognized for application <file-path>:
- ELF binary matching ArchC specifications
- hexadecimal text file for ArchC



Binary utilities
----------------
To generate binary utilities use:

acbingen.sh -i<abs-install-path> -a<arch-name> armv5e.ac

This will generate the tools source files using the architecture
name <arch-name> (if omitted, armv5e is used), copy them to the
binutils source tree, build and install them into the directory
<abs-install-path> (which -must- be an absolute path).
Use "acbingen.sh -h" to get information about the command-line
options available.


Change history
------------

See [History](HISTORY.md)


Contributing
------------

See [Contributing](CONTRIBUTING.md)


More
----

Remember that ArchC models and SystemC library must be compiled with
the same GCC version, otherwise you will get compilation problems.

Several documents which further information can be found in the 'doc'
subdirectory.

You can find language overview, models, and documentation at
http://www.archc.org



Thanks for the interest. We hope you enjoy using ArchC!

The ArchC Team
Computer Systems Laboratory (LSC)
IC-UNICAMP
http://www.lsc.ic.unicamp.br
18 changes: 18 additions & 0 deletions pdl/arm/ac_rtld.relmap
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# This file contains a one-to-one mapping between ARM ABI relocation
# codes and ArchC's generated linker relocation codes. Its intended
# use is to perform a conversion using the acrelconvert tool.

# R_ARM_RELATIVE
23 = 1
# R_ARM_COPY
20 = 2
# R_ARM_JUMPSLOT
22 = 3
# R_ARM_GLOBDAT
21 = 4
# R_ARM_ABS32
2 = 7
# R_ARM_REL32
3 = 10

# End of file
39 changes: 39 additions & 0 deletions pdl/arm/arm.ac
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/**
* @file arm.ac
* @author Danilo Marcolin Caravana
* Rafael Auler
*
* The ArchC Team
* http://www.archc.org/
*
* Computer Systems Laboratory (LSC)
* IC-UNICAMP
* http://www.lsc.ic.unicamp.br/
*
* @version 1.0
* @date Apr 2012
*
* @brief The ArchC ARMv5e functional model.
*
* @attention Copyright (C) 2002-2012 --- The ArchC Team
*
*/

AC_ARCH(arm){
ac_mem MEM:512M;
ac_regbank RB:16;
// ac_tlm_intr_port inta; // system level interrupt port
ac_reg R14_irq, R14_fiq, R14_svc, R14_abt, R14_und, R13_irq, R13_svc;
ac_reg R13_abt, R13_und, R13_fiq;
ac_reg SPSR_irq, SPSR_fiq, SPSR_svc, SPSR_abt, SPSR_und;
// FIQ private regs
ac_reg R12_fiq, R11_fiq, R10_fiq, R9_fiq, R8_fiq;
ac_wordsize 32;
ac_reg id;
ARCH_CTOR(arm) {
ac_isa("arm_isa.ac");
ac_gdb("arm.xml");
defines_gdb("defines_gdb");
set_endian("little");
};
};
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