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RISC-V: add R_RISCV_32 and R_RISCV_64 relocations
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janvrany committed Nov 28, 2024
1 parent cebbde2 commit 2969acf
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41 changes: 41 additions & 0 deletions src/ArchC-RISCV/R_RISCV_32.class.st
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Class {
#name : #'R_RISCV_32',
#superclass : #AcRelocation,
#pools : [
'AcIntLimits'
],
#category : #'ArchC-RISCV-Relocations'
}

{ #category : #queries }
R_RISCV_32 class >> isValidForInstruction: insn [
^ insn class == AcInt32
and: [ insn isa architectureName = 'riscv32' ]
]

{ #category : #'processing - simplified' }
R_RISCV_32 >> calculateS: s A: a P: p [
"
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#relocations
32-bit relocation
"
| v |

v := s + a.

(v between: UINT32_MIN and: UINT32_MAX) ifFalse:[ ^ AddressOutOfRange ].

^ v
]

{ #category : #'processing - simplified' }
R_RISCV_32 >> fixup: memory at: address with: value [
| addr |

addr := ByteArray new: 4.
addr unsignedLongAt: 1 put: value.

memory replaceFrom: address to: address + 4 - 1 with: addr.
]
41 changes: 41 additions & 0 deletions src/ArchC-RISCV/R_RISCV_64.class.st
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@@ -0,0 +1,41 @@
Class {
#name : #'R_RISCV_64',
#superclass : #AcRelocation,
#pools : [
'AcIntLimits'
],
#category : #'ArchC-RISCV-Relocations'
}

{ #category : #queries }
R_RISCV_64 class >> isValidForInstruction: insn [
^ insn class == AcInt64
and: [ insn isa architectureName = 'riscv64' ]
]

{ #category : #'processing - simplified' }
R_RISCV_64 >> calculateS: s A: a P: p [
"
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#relocations
64-bit relocation
"
| v |

v := s + a.

(v between: UINT64_MIN and: UINT64_MAX) ifFalse:[ ^ AddressOutOfRange ].

^ v
]

{ #category : #'processing - simplified' }
R_RISCV_64 >> fixup: memory at: address with: value [
| addr |

addr := ByteArray new: 8.
addr unsignedLongLongAt: 1 put: value.

memory replaceFrom: address to: address + 8 - 1 with: addr.
]

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