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Do not limit async priority with NVIC_PRIO_BITS when targeting ESP32-C3 #996

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merged 2 commits into from
Nov 27, 2024

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jessebraham
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Since RISC-V devices do not have an NVIC, we set the nvicPrioBits field in our SVDs simply to 0. As such, this value should not be used to determine the maximum async priority, and I have aligned the codegen bindings for this target with the riscv_slic version.

@jessebraham jessebraham force-pushed the fixes/esp32c3-codegen-bindings branch from 5829525 to 9b245db Compare November 22, 2024 09:26
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Sorry, forgot I had a PR open with this branch and force pushed 😅

@jessebraham jessebraham force-pushed the fixes/esp32c3-codegen-bindings branch from 9b245db to 912a6be Compare November 22, 2024 09:29
@korken89 korken89 added this pull request to the merge queue Nov 27, 2024
Merged via the queue into rtic-rs:master with commit 8678d42 Nov 27, 2024
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2 participants