Relaxed I/O adheres to Appendix A 4.2

src/machine.tex

@@ -2703,15 +2703,15 @@ \subsection{Memory-Ordering PMAs}
 requests in the main memory system (e.g., DMA engines).  Main memory
 regions always have either the RVWMO or RVTSO memory model.
 
-Accesses by one hart to the I/O space are observable not only by other
-harts and bus mastering devices, but also by targeted slave I/O
-devices.  Within I/O, regions may further be classified as
-implementing either {\em relaxed} or {\em strong} ordering.  A relaxed
-I/O region has no ordering guarantees on how memory accesses made by
-one hart are observable by different harts or I/O devices beyond those
-enforced by FENCE and AMO instructions.  A strongly ordered I/O region
-ensures that all accesses made by a hart to that region are only
-observable in program order by all other harts or I/O devices.
+Accesses by one hart to an I/O region are observable not only by other harts
+and bus mastering devices but also by targeted slave I/O devices, and I/O
+regions may be accessed with either {\em relaxed} or {\em strong} ordering.
+Accesses to an I/O region with relaxed ordering are generally observed by
+other harts and bus mastering devices in a manner similar to the ordering of
+accesses to an RVWMO memory region, as discussed in Section A.4.2 in Volume
+I of this specification.
+By contrast, accesses to an I/O region with strong ordering are generally
+observed by other harts and bus mastering devices in program order.
 
 Each strongly ordered I/O region specifies a numbered ordering
 channel, which is a mechanism by which ordering guarantees can be

src/priv-preface.tex

@@ -32,6 +32,9 @@ \chapter{Preface}
   \itemsep 1pt
 \item Defined the RV32-only CSR {\tt mstatush}, which contains most of the
   same fields as the upper 32 bits of RV64's {\tt mstatus}.
+\item Relaxed I/O regions have been specified to follow RVWMO.  The previous
+  specification implied that PPO rules other than fences and acquire/release
+  annotations did not apply.
 \item Revised the hypervisor architecture proposal to represent VS-mode CSR
   state more simply.
 \item Added optional big-endian and bi-endian support.