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Static Timing Analyzer for validating digital circuits timing from HDL files using C++, Spring 18

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Static_Timing_Analyzer

Static Timing Analyzer for validating digital circuits timing from HDL files using C++. Spring 18.

To Run the DAG: ./out To Compile the project : g++ -std=c++11 DAGcreator.cpp -o out

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Static Timing Analyzer for validating digital circuits timing from HDL files using C++, Spring 18

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