Improvements and refactoring in stdlib and verilog backend

• Add several new test utility components to stdlib
• Improve run_sim and run_vector_sim, refactor plugin options
• Refactor all the tests to use the improved test utility functions
• Add finalize_verilator to run_sim and vector sims
• Rework several parts of RTLIR to accelerate translation
• Drastically improved verilator import performance and compilation time
• Accelerated the dynamic compilation of ff_flip