add todo for get instr bytes

purseclab · Mar 7, 2024 · 97d92a8 · 97d92a8
1 parent 73b5e52
commit 97d92a8
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Showing 11 changed files with 12 additions and 0 deletions.
diff --git a/src/patcherex2/components/archinfo/aarch64.py b/src/patcherex2/components/archinfo/aarch64.py
@@ -5,6 +5,7 @@ class Aarch64Info:
     jmp_size = 4
     alignment = 4
     is_variable_length_isa = False
+    instr_size = 4
     call_asm = "bl {dst}"
     pc_reg_names = ["pc", "ip"]
     save_context_asm = """

diff --git a/src/patcherex2/components/archinfo/amd64.py b/src/patcherex2/components/archinfo/amd64.py
@@ -5,6 +5,7 @@ class Amd64Info:
     jmp_size = 6
     alignment = 4
     is_variable_length_isa = True
+    instr_size = -1 # variable length
     call_asm = "call {dst}"
     pc_reg_names = ["rip"]
     save_context_asm = """

diff --git a/src/patcherex2/components/archinfo/arm.py b/src/patcherex2/components/archinfo/arm.py
@@ -5,6 +5,7 @@ class ArmInfo:
     jmp_size = 4
     alignment = 4
     is_variable_length_isa = False
+    instr_size = 4 # TODO: thumb 2
     call_asm = "bl {dst}"
     pc_reg_names = ["pc", "r15", "ip"]
     save_context_asm = """

diff --git a/src/patcherex2/components/archinfo/mips.py b/src/patcherex2/components/archinfo/mips.py
@@ -6,6 +6,7 @@ class MipsInfo:
     jmp_size = 8
     alignment = 4
     is_variable_length_isa = False
+    instr_size = 4
     call_asm = "jal {dst}"
     pc_reg_names = ["pc"]
     save_context_asm = """

diff --git a/src/patcherex2/components/archinfo/mips64.py b/src/patcherex2/components/archinfo/mips64.py
@@ -6,6 +6,7 @@ class Mips64Info:
     jmp_size = 8
     alignment = 4
     is_variable_length_isa = False
+    instr_size = 4
     call_asm = "jal {dst}"
     pc_reg_names = ["pc"]
     save_context_asm = """

diff --git a/src/patcherex2/components/archinfo/ppc.py b/src/patcherex2/components/archinfo/ppc.py
@@ -5,6 +5,7 @@ class PpcInfo:
     jmp_size = 4
     alignment = 4
     is_variable_length_isa = False
+    instr_size = 4
     call_asm = "bl {dst}"
     pc_reg_names = []
     save_context_asm = """

diff --git a/src/patcherex2/components/archinfo/ppc64.py b/src/patcherex2/components/archinfo/ppc64.py
@@ -5,6 +5,7 @@ class Ppc64Info:
     jmp_size = 4
     alignment = 4
     is_variable_length_isa = False
+    instr_size = 4
     call_asm = "bl {dst}"
     pc_reg_names = []
     save_context_asm = """

diff --git a/src/patcherex2/components/archinfo/ppc_vle.py b/src/patcherex2/components/archinfo/ppc_vle.py
@@ -5,6 +5,7 @@ class PpcVleInfo:
     jmp_size = 4
     alignment = 4
     is_variable_length_isa = True
+    instr_size = -1  # variable length
     call_asm = "bl {dst}"
     pc_reg_names = []
     save_context_asm = ""  # TODO

diff --git a/src/patcherex2/components/archinfo/sparc.py b/src/patcherex2/components/archinfo/sparc.py
@@ -5,6 +5,7 @@ class SparcInfo:
     jmp_size = 8
     alignment = 4
     is_variable_length_isa = False
+    instr_size = 4
     call_asm = "call {dst}"
     pc_reg_names = ["pc"]
     save_context_asm = ""  # TODO

diff --git a/src/patcherex2/components/archinfo/x86.py b/src/patcherex2/components/archinfo/x86.py
@@ -5,6 +5,7 @@ class X86Info:
     jmp_size = 5
     alignment = 4
     is_variable_length_isa = True
+    instr_size = -1 # variable length
     call_asm = "call {dst}"
     pc_reg_names = ["eip"]
     save_context_asm = """

diff --git a/src/patcherex2/components/binary_analyzers/angr.py b/src/patcherex2/components/binary_analyzers/angr.py
@@ -89,6 +89,8 @@ def get_basic_block(self, addr: int) -> Dict[str, Union[int, List[int]]]:
     def get_instr_bytes_at(self, addr: int, num_instr=1) -> angr.Block:
         addr += 1 if self.is_thumb(addr) else 0
         addr = self.denormalize_addr(addr)
+        # TODO: Special handling for delay slot, when there is a call instr with delay slot
+        # angr will return both instrs, even when num_instr is 1
         return self.p.factory.block(addr, num_inst=num_instr).bytes
 
     def get_unused_funcs(self) -> List[Dict[str, int]]: