Add support for VCU118 block design #287

CyrilKoe · 2025-01-17T09:21:15Z

Added VCU118 block design and device tree
Removed half-done hyperram support (kept in other working branch) (pads are still in the Carfield IP but unconnected in the flow)
Added BD constraints for VCU118 (including ext_jtag)
Added CI boot for VCU118
Migrated CI to the new bordcomputer server

Tests:

CyrilKoe · 2025-01-18T10:22:00Z

carfield.mk

docs/tg/xilinx.md

sw/boot/carfield_bd_vcu118.dts

target/xilinx/flavor_bd/scripts/carfield_bd_vcu118.tcl

target/xilinx/flavor_vanilla/constraints/vcu128_ext_jtag.xdc

target/xilinx/flavor_vanilla/flavor_vanilla.mk

alex96295

I added some minor comments, good job and thank you for the PR

As a side note, let's make sure we merge the nonfree branch before this

alex96295

LGTM

CyrilKoe added 15 commits June 14, 2024 12:25

fpga: Testing hyperram in block design

e5c4073

fpga: Testing hyperram in vanilla

86153e6

fpga: Correct Xilinx IP verilog to follow the standard

cdfeabc

fpga: Adding hyperram CDC constraints

22c651f

fpga: Adding pads in vanilla

862913e

fpga: Adding vcu118 BD support

c0bc77c

fpga: Cleaning PR

742bc6a

vcu118: Ethernet debug

843766a

docs: Updated Xilinx targets

eaa86e5

fpga: Removed hyperbus for this PR

1eda45e

fpga: CI and flash script

daec5c8

fpga: Debug once again spi

7df6ba6

fpga: Changing STARTUPE3 tie-off

91f1ae5

fpga: Reset board after program

4fc1c91

sw: New dts for vcu118

1d27e86

CyrilKoe self-assigned this Jan 17, 2025

ci: Update for FPGA

db46b35

CyrilKoe force-pushed the ck/vcu118 branch from 4e3dac2 to db46b35 Compare January 17, 2025 15:02

CyrilKoe marked this pull request as ready for review January 18, 2025 10:21

CyrilKoe requested a review from alex96295 as a code owner January 18, 2025 10:21

CyrilKoe changed the title ~~Draft: Add support for VCU118 block design~~ Add support for VCU118 block design Jan 18, 2025