misc: Update docs and licenses

pulp-platform · Jan 23, 2025 · 6beaf13 · 6beaf13
1 parent db46b35
commit 6beaf13
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diff --git a/docs/tg/xilinx.md b/docs/tg/xilinx.md
@@ -11,6 +11,8 @@ We currently provide working setups for:
 - Xilinx VCU128 with Vivado `== 2020.2`
 - Xilinx VCU118 with Vivado `== 2020.2`
 
+:warning: At the moment it is required to use the Vivado version above
+
 **Note: Certain version of Vivado might cause issue, until these issues are resolved it is safer to use 2020.2**
 
 We are working on support for more boards in the future.
@@ -27,7 +29,7 @@ design flow to link Carfield with external IPs. This flow is less human readable
 integrating more complex IPs as Xilinx Ethernet. *Note that this may require you to own the
 respective licenses.*
 
-## For impatient readers
+## Quick Start
 
 The recommended command to build a bitstream (for VCU128) is
 
@@ -158,7 +160,7 @@ JTAG chain to connect GDB to the debug-module in the bitstream.
 using the Xilinx BSCANE macro. With this, you will only need the normal Xilinx USB cable to interact
 with CVA6. Note that it means that
 Vivado and OpenOCD can not use the same cable at the same time.
->**WARNING: this setup (with `EXT_JTAG=0`) will only work for designs containing the host only** as
+> :warning: This setup (with `EXT_JTAG=0`) will only work for designs containing the host only** as
 it is not possible to chain multiple devices on the BSCANE macro. If you need to use `EXT_JTAG=0`
 consider modifying the RTL to remove the debug modules of the IPs.
 > When using `EXT_JTAG=1` we add an external JTAG chain for the RV64 host and other island through

diff --git a/sw/boot/carfield_bd_vcu118.dts b/sw/boot/carfield_bd_vcu118.dts
@@ -1,4 +1,4 @@
-// Copyright 2022 ETH Zurich and University of Bologna.
+// Copyright 2025 ETH Zurich and University of Bologna.
 // Solderpad Hardware License, Version 0.51, see LICENSE for details.
 // SPDX-License-Identifier: SHL-0.51
 //

diff --git a/target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc b/target/xilinx/flavor_bd/constraints/vcu118_ext_jtag.xdc
@@ -1,4 +1,4 @@
-# Copyright 2024 ETH Zurich and University of Bologna.
+# Copyright 2025 ETH Zurich and University of Bologna.
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 #

diff --git a/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc b/target/xilinx/flavor_bd/constraints/vcu128_ext_jtag.xdc
@@ -1,4 +1,4 @@
-# Copyright 2024 ETH Zurich and University of Bologna.
+# Copyright 2025 ETH Zurich and University of Bologna.
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 #

diff --git a/target/xilinx/flavor_vanilla/flavor_vanilla.mk b/target/xilinx/flavor_vanilla/flavor_vanilla.mk
@@ -46,7 +46,7 @@ $(CAR_XIL_DIR)/flavor_vanilla/scripts/add_sources.tcl: Bender.yml
 
 # Compile bitstream
 $(CAR_XIL_DIR)/flavor_vanilla/out/%.bit: $(xilinx_ips_paths_vanilla) $(CAR_XIL_DIR)/flavor_vanilla/scripts/add_sources.tcl
-	@if [ "$(GEN_NO_HYPERBUS)" != "1" ] && [ "$(XILINX_ELABORATION_ONLY)" != "1" ]; then echo "Hyperbus not supported yet in this branch"; fi;
+	@if [ "$(GEN_NO_HYPERBUS)" != "1" ] && [ "$(XILINX_ELABORATION_ONLY)" != "1" ]; then echo "Support for the Hyperbus FMC card is not yet available."; fi;
 	@mkdir -p $(CAR_XIL_DIR)/flavor_vanilla/out
 	cd $(CAR_XIL_DIR)/flavor_vanilla && $(vivado_env) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run.tcl
 	find $(CAR_XIL_DIR)/flavor_vanilla/carfield* -name "*.ltx" -o -name "*.bit" -o -name "*routed.rpt" | xargs -I {} cp {} $(CAR_XIL_DIR)/flavor_vanilla/out