Repositories list

• server-soc

  Public
  The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.

  TeX

  •

  Creative Commons Attribution 4.0 International

  •12•26•2•0•Updated Sep 17, 2025Sep 17, 2025

• riscv-sbi-doc

  Public
  Documentation for the RISC-V Supervisor Binary Interface

  Makefile

  •

  Creative Commons Attribution 4.0 International

  •97•427•13•2•Updated Sep 17, 2025Sep 17, 2025

• riscv-rpmi

  Public
  RISC-V Platform Management Interface Specification. OS-agnostic messaging interface for system management and control

  platformmessagingstandards+ 4interoperabilityriscvrpmiriscv-rpmi

  Makefile

  •

  Creative Commons Attribution 4.0 International

  •12•13•2•2•Updated Sep 17, 2025Sep 17, 2025

• riscv-asm-manual

  Public
  RISC-V Assembly Programmer's Manual

  Makefile

  •

  Creative Commons Attribution 4.0 International

  •248•1.6k•9•9•Updated Sep 17, 2025Sep 17, 2025

• riscv-iommu

  Public
  RISC-V IOMMU Specification

  C

  •

  Creative Commons Attribution 4.0 International

  •27•129•1•2•Updated Sep 17, 2025Sep 17, 2025

• iopmp-spec

  Public
  This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protection Unit of Input/Output devices, IOPMP for short, to regulate the accesses issued from the bus masters.

  C

  •

  Creative Commons Attribution 4.0 International

  •9•33•0•1•Updated Sep 17, 2025Sep 17, 2025

• riscv-toolchain-conventions

  Public
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains

  Makefile

  •

  Creative Commons Attribution 4.0 International

  •42•152•10•1•Updated Sep 17, 2025Sep 17, 2025

• riscv-cbqri

  Public
  This repo holds the work area and revisions of a QoS register interface for caches and memory controllers specification. The QoS register interface is a non-ISA specification that supports configuring resource allocations to applications and monitoring the resource usage by applications.

  Makefile

  •

  Creative Commons Attribution 4.0 International

  •10•7•0•0•Updated Sep 17, 2025Sep 17, 2025

• hart-trace-interface

  Public
  This Fast-Track will extract the Hart-Trace Interface chapter from the E-Trace spec and turn it into a standalone spec

  Makefile

  •

  Creative Commons Attribution 4.0 International

  •2•1•6•4•Updated Sep 17, 2025Sep 17, 2025

• riscv-ras-eri

  Public
  The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and confi…

  TeX

  •

  Creative Commons Attribution 4.0 International

  •8•10•0•1•Updated Sep 17, 2025Sep 17, 2025

• riscv-security-model

  Public
  RISC-V Security Model

  Makefile

  •

  Creative Commons Attribution 4.0 International

  •17•32•0•1•Updated Sep 17, 2025Sep 17, 2025

• riscv-semihosting

  Public
  Makefile

  •

  Creative Commons Attribution Share Alike 4.0 International

  •12•32•2•2•Updated Sep 17, 2025Sep 17, 2025

• riscv-acpi-rimt

  Public
  RISC-V ACPI I/O Mapping Table Specification

  Makefile

  •

  Creative Commons Attribution 4.0 International

  •4•6•1•1•Updated Sep 17, 2025Sep 17, 2025

• riscv-c-api-doc

  Public
  Documentation of the RISC-V C API

  Makefile

  •

  Creative Commons Attribution 4.0 International

  •47•77•17•4•Updated Sep 17, 2025Sep 17, 2025

• riscv-brs

  Public
  The Boot and Runtime Services (BRS) specification provides the software requirements for system vendors and Operating System Vendors (OSVs) to interoperate with one another by providing expectations for the Operating System (OS) to utilize in acts of device discovery, system management, and other rich operations provided in this specification.

  platformfirmwarestandards+ 9interoperabilityuefidevicetreeacpismbiosrisc-vbrs-i+ 2

  TeX

  •

  Creative Commons Attribution 4.0 International

  •20•53•15•1•Updated Sep 17, 2025Sep 17, 2025

• riscv-external-debug-security

  Public
  The RISC-V External Debug Security Specification

  Makefile

  •

  Creative Commons Attribution 4.0 International

  •4•20•0•2•Updated Sep 17, 2025Sep 17, 2025

• riscv-server-platform

  Public
  The RISC-V Server Platform specification defines a standardized set of hardware and sofware capabilities, that portable system software, such as operating systems and hypervisors, can rely on being present in a RISC-V server platform.

  platformserveros+ 9standardsinteroperabilityuefihypervisorsacpirisc-vbrs-i+ 2

  TeX

  •

  Creative Commons Attribution 4.0 International

  •13•19•5•0•Updated Sep 10, 2025Sep 10, 2025

• riscv-ap-tee-io

  Public
  This TG will define AP-TEE-IO ABI extensions to provide Confidential VM-assigned devices with secure direct access to confidential memory as well as MMIO, removing the dependence on para-virtualized I/O.

  tee-io

  Makefile

  •

  Creative Commons Attribution 4.0 International

  •5•14•10•1•Updated Sep 9, 2025Sep 9, 2025

• riscv-elf-psabi-doc

  Public
  A RISC-V ELF psABI Document

  Python

  •

  Creative Commons Attribution 4.0 International

  •178•802•63•28•Updated Sep 8, 2025Sep 8, 2025

• rvv-intrinsic-doc

  Public
  C

  •

  BSD 3-Clause "New" or "Revised" License

  •103•345•26•9•Updated Sep 5, 2025Sep 5, 2025

• riscv-acpi-ffh

  Public
  The repo will be used to hold the draft non-ISA RISC-V ACPI Functional Fixed Hardware (FFH) specification

  Makefile

  •

  Creative Commons Attribution 4.0 International

  •6•5•2•2•Updated Aug 28, 2025Aug 28, 2025

• e-trace-encap

  Public
  E-Trace Encapsulation Specification

  Makefile

  •

  Creative Commons Attribution 4.0 International

  •4•7•0•1•Updated Aug 28, 2025Aug 28, 2025

• riscv-arch-test

  Public
  Assembly

  •

  Apache License 2.0

  •235•591•63•44•Updated Aug 28, 2025Aug 28, 2025

• riscv-trace-spec

  Public
  RISC-V Processor Trace Specification

  C

  •

  Creative Commons Attribution 4.0 International

  •57•193•13•4•Updated Aug 4, 2025Aug 4, 2025

• riscv-rqsc

  Public
  Specification Documentation Repository for the RQSC RISC-V Quality of Services Controllers Table definition

  Makefile

  •

  Creative Commons Attribution 4.0 International

  •1•0•0•1•Updated Jul 1, 2025Jul 1, 2025

• riscv-ap-tee

  Public
  This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the programming interfaces (ABI) to support the Confidential VM Extension (CoVE) confidential computing architecture for RISC-V application-processor platforms.

  securityvirtualizationtee+ 6tsmconfidential-computingconfidential-vmh-extensionsmmttsupervisor-domains

  Makefile

  •

  Creative Commons Attribution 4.0 International

  •23•60•23•0•Updated May 13, 2025May 13, 2025

• server-soc-ts

  Public
  Test suite for Server SoC

  C

  •

  Apache License 2.0

  •8•5•2•2•Updated Mar 29, 2025Mar 29, 2025

• tg-nexus-trace

  Public
  RISC-V Nexus Trace TG documentation and reference code

  nexustracerisc-v

  C

  •

  Creative Commons Attribution 4.0 International

  •38•52•12•2•Updated Jan 3, 2025Jan 3, 2025

• riscv-arch-test-reports

  Public
  HTML

  •6•11•0•0•Updated Dec 2, 2024Dec 2, 2024

• riscv-device-tree-doc

  Public
  RISC-V Specific Device Tree Documentation

  Python

  •3•42•1•1•Updated Jul 9, 2024Jul 9, 2024