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    298 repositories

    • ri5cy_gnu_toolchain

      Public archive
      Makefile
      •23•23•15•3•Updated Mar 15, 2025Mar 15, 2025

    • riscv-gcc

      Public archive
      GNU GCC for PULP and RISC-V
      C
      •
      GNU General Public License v2.0
      •1•1•2•0•Updated Mar 15, 2025Mar 15, 2025

    • pulp-riscv-gcc

      Public archive
      C
      •
      Other
      •18•7•1•1•Updated Mar 15, 2025Mar 15, 2025

    • llvm-project

      Public
      C++
      •13k•7•7•1•Updated Mar 15, 2025Mar 15, 2025

    • pulp-riscv-gnu-toolchain

      Public
      C
      •
      Other
      •52•78•26•0•Updated Mar 15, 2025Mar 15, 2025

    • riscv-gnu-toolchain

      Public
      GNU toolchain for PULP and RISC-V
      C
      •
      Other
      •8•10•0•2•Updated Mar 15, 2025Mar 15, 2025

    • redmule

      Public
      SystemVerilog
      •
      Other
      •13•49•1•5•Updated Mar 14, 2025Mar 14, 2025

    • pulpissimo

      Public
      This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
      SystemVerilog
      •
      Other
      •174•404•124•4•Updated Mar 14, 2025Mar 14, 2025

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •36•42•7•4•Updated Mar 14, 2025Mar 14, 2025

    • fscil

      Public
      Python
      •
      Apache License 2.0
      •0•6•0•0•Updated Mar 14, 2025Mar 14, 2025

    • eae-kws

      Public
      Python
      •
      Apache License 2.0
      •0•1•0•0•Updated Mar 14, 2025Mar 14, 2025

    • MI-BMInet

      Public
      This repository contains the development of Q-EEGNet from training to quantization and finally to the implementation on Mr. Wolf.
      Shell
      •1•0•0•0•Updated Mar 14, 2025Mar 14, 2025

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •55•232•10•20•Updated Mar 14, 2025Mar 14, 2025

    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •12•28•8•3•Updated Mar 14, 2025Mar 14, 2025

    • control-pulp

      Public
      C
      •
      Other
      •2•3•1•1•Updated Mar 14, 2025Mar 14, 2025

    • picobello

      Public
      whatever it means
      SystemVerilog
      •
      Other
      •0•5•7•0•Updated Mar 14, 2025Mar 14, 2025

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •739•19•0•5•Updated Mar 14, 2025Mar 14, 2025

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •13•63•1•2•Updated Mar 14, 2025Mar 14, 2025

    • pulp_hpc_cosim

      Public
      C
      •
      Apache License 2.0
      •0•0•0•0•Updated Mar 14, 2025Mar 14, 2025

    • control_pulp_pcf

      Public
      C
      •
      Apache License 2.0
      •0•0•0•0•Updated Mar 14, 2025Mar 14, 2025

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •140•408•70•6•Updated Mar 13, 2025Mar 13, 2025

    • regression_tests

      Public
      C
      •17•8•3•1•Updated Mar 13, 2025Mar 13, 2025

    • safety_island

      Public
      A reliable, real-time subsystem for the Carfield SoC
      C
      •
      Other
      •4•14•1•4•Updated Mar 13, 2025Mar 13, 2025

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •49•288•3•5•Updated Mar 12, 2025Mar 12, 2025

    • chimera

      Public
      Python
      •
      Other
      •3•16•9•3•Updated Mar 12, 2025Mar 12, 2025

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •4•11•1•4•Updated Mar 12, 2025Mar 12, 2025

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •60•69•16•7•Updated Mar 12, 2025Mar 12, 2025

    • pulp-ethernet

      Public
      SystemVerilog
      •
      Other
      •1•11•0•2•Updated Mar 12, 2025Mar 12, 2025

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •21•99•1•4•Updated Mar 12, 2025Mar 12, 2025

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •23•83•5•3•Updated Mar 11, 2025Mar 11, 2025