Add AW lock register to handle W FIFO push signal

[ricted98]

The original implementation uses the AW handshake as the logical condition for a push into the W channel FIFO. However, this choice implicitly assume that the AW handshake will take place concurrently or before the W channel handshake.

This assumption is not mandatory in the AXI standard and a downstream IP can generate a situation where the W channel handshake precedes the AW channel one, resulting in a pop of a potentially empty FIFO.

Using an AW lock register to control the pushes on the FIFO makes sure that the proper W selection is stored as soon as the core generates a valid AW request (aw_valid = 1'b1) without relying on the occurrence of an AW handshake, which can happen out of order.

This specific situation was observed when using CVA6 with a downstream AXI ID serializer. Due to the serializer internal FIFOs being full, the AW request was gated but the W channel was passed through, thus generating the situation where the core observed aw_ready = 1'b0 and w_ready = 1'b1 and the empty W FIFO was popped.

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	always_ff @( posedge clk_i or negedge rst_ni ) begin : aw_lock_reg
	always_ff @(posedge clk_i or negedge rst_ni) begin : aw_lock_reg

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	else aw_lock_q <= aw_lock_d;
	else aw_lock_q <= aw_lock_d;

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	assign w_fifo_pop = axi_req_o.w_valid & axi_resp_i.w_ready & axi_req_o.w.last;
	assign aw_lock_d = ~axi_resp_i.aw_ready & (axi_req_o.aw_valid | aw_lock_q);
	assign w_fifo_pop = axi_req_o.w_valid & axi_resp_i.w_ready & axi_req_o.w.last;
	assign aw_lock_d = ~axi_resp_i.aw_ready & (axi_req_o.aw_valid | aw_lock_q);

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[github-actions]

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[github-actions]

✔️ successful run, report available here.