CEP Release v2.51

README.md

@@ -4,7 +4,7 @@
     <img src="./cep_logo.jpg">
 </p>
 <p align="center">
-   v2.5
+   v2.51
    <br>
    Copyright 2020 Massachusetts Institute of Technology
 </p>
@@ -163,7 +163,7 @@ Install the required dependencies by running the following command:
 
 As one might be aware: the endianess usage is not consistent thru out the design, expesially where Chisel wrappers are used to connect to various HW cores. For some cores, little endian is used for loading keys/plain text but big-endian is used to produce cipher text as output. This creates confusion and inconsistent as one might try to understand/follow SW driver for these cores. Also, please note, RISCV is little endian.
 
-As of this release CEP v2.4 and later, unless otherwise specify, big endian is used thru out the design to match key/plain/ciphertext network order.
+As of release CEP v2.4 and later, unless otherwise specify, big endian is used thru out the design to match key/plain/ciphertext network order.
 This makes it consistent and easier to debug when key/plain text are printed to match against registers.
 
 ```
@@ -282,7 +282,7 @@ You should see the following logo/text appear:
   ./+++++++++++oo+++:  +oo++o++++o+o+oo+oo.- `s+++s`-           
     .--:---:-:-::-::`  -::::::::::::::::::.   :::::.            
                                                                 
-              Common Evaluation Platform v2.5                   
+              Common Evaluation Platform v2.51
   Copyright (C) 2020 Massachusetts Institute of Technology     
                                                                 
        Built upon the SiFive Freedom U500 Platform using        
@@ -310,7 +310,7 @@ At the command prompt, you can run the CEP diagnostics by commanding `cep_diag`.
 A partial output should be similar to:
 
 ```sh
-*** CEP Tag=CEPTest CEP HW VERSION = v2.5 was built on May 15 2020*
+*** CEP Tag=CEPTest CEP HW VERSION = v2.51 was built on May 15 2020*
  CEP FPGA Physical=0x70000000 -> Virtual=0x000000200034d000
 gSkipInit=0/0
 gverbose=0/0
@@ -446,6 +446,9 @@ v2.5 - (31 July 2020)
 * All Unit-level testbenches have been expanded to optional support the Logic Locking Keying Interface (LLKI)
   for both cycle-level and transactional-level modes
 
+v2.51 - (7 August 2020)
+* Legacy unused core wrapper files (axi4lite and wb) removed
+
 ## Licensing
 The CEP been developed with a goal of using components with non-viral, open source licensing whenever possible.  When not feasible (such as Linux), pointers to reference repositories are given using the [get_external_dependencies.sh](./get_external_dependencies.sh) script.  
 

cosim/drivers/linux/cep_diag.cc

@@ -85,7 +85,7 @@ void lnx_mem_write(u_int32_t offs,u_int64_t pData) {
 // =======================================
 //
 static void Print_CepBuildDate(void) {
-  printf("\n*** CEP Tag=%s CEP HW VERSION = v%d.%d was built on %s %s ***\n",
+  printf("\n*** CEP Tag=%s CEP HW VERSION = v%x.%x was built on %s %s ***\n",
    CEP_TAG, MAJOR_VERSION(lnx_cep_read(CEP_VERSION_REG)), MINOR_VERSION(lnx_cep_read(CEP_VERSION_REG)),__DATE__,__TIME__);
   // do the read and print
   printf(" CEP FPGA Physical=0x%08x -> Virtual=0x%016lx\n",(u_int32_t)_cepMap.phy_address,(u_int64_t)_cepMap.mem);

cosim/dvt/cep_adrMap.incl

@@ -74,7 +74,7 @@
 //
 `define	reg_base_addr           'h700F_0000
 `define   CEP_VERSION_REG		'h700F_0000
-`define CEP_EXPECTED_VERSION 	'h05020000_00000000
+`define CEP_EXPECTED_VERSION 	'h51020000_00000000
 `define CEP_VERSION_MASK     	'h0FFFFFFF_FFFFFFFF
 //
 // Test and Set