CEP Release v2.61

README.md

@@ -5,7 +5,7 @@
     <img src="./cep_logo.jpg">
 </p>
 <p align="center">
-   v2.6
+   v2.61
    <br>
    Copyright 2020 Massachusetts Institute of Technology
 </p>
@@ -280,7 +280,7 @@ You should see the following logo/text appear:
        ./+++++++++++oo+++:  +oo++o++++o+o+oo+oo.- `s+++s`-
        .--:---:-:-::-::`  -::::::::::::::::::.   :::::.
 
-                      Common Evaluation Platform v2.6
+                     Common Evaluation Platform v2.61
          Copyright (C) 2020 Massachusetts Institute of Technology
 
             Built upon the SiFive Freedom U500 Platform using
@@ -303,7 +303,7 @@ At the command prompt, you can run the CEP diagnostics by commanding `cep_diag`.
 A partial output should be similar to:
 
 ```sh
-*** CEP Tag=CEPTest CEP HW VERSION = v2.60 was built on Sep 17 2020 12:01:26 ***
+*** CEP Tag=CEPTest CEP HW VERSION = v2.61 was built on Sep 17 2020 12:01:26 ***
  CEP FPGA Physical=0x70000000 -> Virtual=0x00000020004fa000
 gSkipInit=0/0
 gverbose=0/0
@@ -441,6 +441,10 @@ v2.6 - (18 September 2020)
 
 	  Functionally, this should only cause an issue when dealing with self-modifying code, which is an atypical coding practice.
 
+v2.61 - (2 October 2020)
+  - Added initial simulation support for Cadence XCellium
+  - Cosim: Expanded DDR3 memory size to support "larger" bare-metal executables created by the new RISCV toolchain released with v2.6
+
 ## Licensing
 The CEP been developed with a goal of using components with non-viral, open source licensing whenever possible.  When not feasible (such as Linux), pointers to reference repositories are given using the [get_external_dependencies.sh](./get_external_dependencies.sh) script.  
 

cosim/bareMetalTests/macroMix/c_dispatch.cc

@@ -48,7 +48,7 @@ int main(int argc, char *argv[])
   //
   // each bit is to turn on the given core (bit0 = core0, bit1=core1, etc..)
   //
-  long unsigned int mask = 0xF;
+  long unsigned int mask = 0xf;
   //
   // Set the active CPU mask before spawn the threads...
   //

cosim/drivers/cep_tests/cep_apis.cc

@@ -196,6 +196,7 @@ int load_mainMemory(char *imageF, uint32_t ddr3_base, int srcOffset, int destOff
   for (i=0;i<4;i++) {
     errCnt += clear_printf_mem(i);
   }
+
   // turn back on
   DUT_WRITE_DVT(DVTF_PAT_HI, DVTF_PAT_LO, 1);
   DUT_WRITE_DVT(DVTF_SET_IPC_DELAY, DVTF_SET_IPC_DELAY, 1);

cosim/dvt/cep_adrMap.incl

@@ -75,7 +75,7 @@
 //
 `define	reg_base_addr           'h700F_0000
 `define   CEP_VERSION_REG		'h700F_0000
-`define CEP_EXPECTED_VERSION 	'h60020000_00000000
+`define CEP_EXPECTED_VERSION 	'h61020000_00000000
 `define CEP_VERSION_MASK     	'h0FFFFFFF_FFFFFFFF
 //
 // Test and Set

cosim/dvt/cep_tb.v

@@ -644,10 +644,11 @@ module cep_tb;
 	 defparam ddr3.DEBUG=0;
 	 defparam ddr3.check_strict_mrbits=0;
 	 defparam ddr3.check_strict_timing=0;
-	 defparam ddr3.MEM_BITS=14;
+	 defparam ddr3.MEM_BITS= 16; // some how the new RISC (v2.6) has a lot more writes (14->16)	 	 
 	 defparam ddr3.TWLS = 2; // to remove the WARNING violation which can't be turned off from outside
 	 defparam ddr3.TWLH = 2; // to remove the WARNING violation   
-
+	 // for RHEL7: access beyond 1G ????
+	 defparam ddr3.STOP_ON_ERROR = 0;
 	 //
 	 // Write Monitor
 	 //

hdl_cores/freedom/bootrom/sdboot/sd.c

@@ -224,7 +224,7 @@ void print_greeting()
     kputs("       ./+++++++++++oo+++:  +oo++o++++o+o+oo+oo.- `s+++s`-                   "); 
     kputs("       .--:---:-:-::-::`  -::::::::::::::::::.   :::::.                      "); 
     kputs("                                                                             ");
-    kputs("                     Common Evaluation Platform v2.6                         ");
+    kputs("                    Common Evaluation Platform v2.61                         ");
     kputs("         Copyright (C) 2020 Massachusetts Institute of Technology            ");
     kputs("                                                                             ");
     kputs("            Built upon the SiFive Freedom U500 Platform using                ");

hdl_cores/freedom/mitll-blocks/src/main/scala/cep_addresses.scala

@@ -11,7 +11,7 @@ package mitllBlocks.cep_addresses
 
 object CEPVersion {
 	val CEP_MAJOR_VERSION		= 0x02
-	val CEP_MINOR_VERSION		= 0x60
+	val CEP_MINOR_VERSION		= 0x61
 }
 
 object CEPBaseAddresses {

unit_simulation/TL_level_sim/Makefile

@@ -1,5 +1,6 @@
 #//************************************************************************
 #// Copyright (C) 2020 Massachusetts Institute of Technology
+#// SPDX License Identifier: MIT
 #//
 #// File Name:      Makefile     
 #// Program:        Common Evaluation Platform (CEP)
@@ -26,6 +27,18 @@ CORE        = aes
 #
 VERBOSE     = 1
 #
+#
+# Add Cadence supports ro tun on RHEL7 machine
+#
+CADENCE  = 0
+ifeq (${CADENCE},1)
+DEFINE_LIST += +define+CADENCE
+export CADENCE_ENABLE_AVSREQ_63188_PHASE_1:=1
+export CADENCE_ENABLE_AVSREQ_44905_PHASE_1:=1
+# also might need to set  as sudo
+#sudo setsebool -P mmap_low_allowed 1
+endif
+
 #
 # -------------------------------------------
 # STOP!!!
@@ -113,11 +126,15 @@ DEFINE_LIST += +define+RANDOMIZE_MEM_INIT
 # ------------------------------------------
 #
 all: ./supports/VCShell_llki.v ./supports/VCShell_llki.v
+ifeq (${CADENCE},1)
+	rm -rf xcelium.d
+	xrun -64 -sv +acc ../llki_supports/llki_discrete.sv  ${DEFINE_LIST} ./supports/tl_unit_tb.sv ${CORE_VFILES} ${OTHERS_FILES} ${SEARCH_DIR} ${INC_DIR} +libext+.v +libext+.sv  -xlm_bq1
+else
 	rm -rf work
 	vlog -64 -sv +acc ${DEFINE_LIST} ./supports/tl_unit_tb.sv ${CORE_VFILES} ${OTHERS_FILES} ${SEARCH_DIR} ${INC_DIR} +libext+.v +libext+.sv 
 	vopt -64 +nolibcell +nospecify +notimingchecks ${TB_NAME} -o ${TB_NAME}_opt
 	vsim -64 ${TB_NAME}_opt -batch -do vsim.do -logfile ${CORE}.log -wlf ${CORE}.wlf
-
+endif
 
 #
 # No LLKI

unit_simulation/aes_sim/Makefile

@@ -1,5 +1,6 @@
 #//************************************************************************
 #// Copyright (C) 2020 Massachusetts Institute of Technology
+#// SPDX License Identifier: MIT
 #//
 #// File Name:      Makefile     
 #// Program:        Common Evaluation Platform (CEP)
@@ -8,6 +9,7 @@
 #//	to run , type "make" 
 #//
 #//************************************************************************
+#
 LLKI_EN      = 1
 
 #
@@ -16,6 +18,16 @@ LLKI_EN      = 1
 USE_MOCK_LLKI   = 1
 CORE_WITH_LLKI = real_aes_192_with_llki
 #
+# Add Cadence supports ro tun on RHEL7 machine
+#
+CADENCE  = 0
+ifeq (${CADENCE},1)
+DEFINE_LIST += +define+CADENCE
+export CADENCE_ENABLE_AVSREQ_63188_PHASE_1:=1
+export CADENCE_ENABLE_AVSREQ_44905_PHASE_1:=1
+# also might need to set  as sudo
+#sudo setsebool -P mmap_low_allowed 1
+endif
 #
 #
 ifeq (${LLKI_EN},0)
@@ -43,14 +55,19 @@ DEFINE_LIST += +define+DUT_NAME=${DUT_NAME} +define+TB_NAME=${TB_NAME}
 #
 #
 all: aes_stimulus.txt
+ifeq (${CADENCE},1)
+	xrun -64 -sv +acc *.sv ${LLKI_FILES} ${DEFINE_LIST} ${CORE_VFILES} -y ../llki_supports +libext+.v +libext+.sv +incdir+../llki_supports -xlm_bq1
+else
 	vlog -64 -sv +acc *.sv ${LLKI_FILES} ${DEFINE_LIST} ${CORE_VFILES} -y ../llki_supports +libext+.v +libext+.sv +incdir+../llki_supports
 	vopt -64 +nolibcell +nospecify +notimingchecks ${TB_NAME} -o ${TB_NAME}_opt
 	vsim -64 ${TB_NAME}_opt -batch -do vsim.do -logfile ${TB_NAME}.log -wlf ${TB_NAME}.wlf
+endif
 
 aes_stimulus.txt : aes_stimulus.txt.gz
 	gunzip -c $< > $@
 
 clean:
-	rm -rf work *.wlf *.log *.txt
+	rm -rf work *.wlf *.log *.txt 
+	rm -rf xcelium.d
 
 

unit_simulation/aes_sim/aes_192_mock_tss.sv

@@ -1,12 +1,13 @@
 //************************************************************************
 // Copyright (C) 2020 Massachusetts Institute of Technology
+// SPDX License Identifier: MIT
 //
 // File Name:      aes_mock_tss.sv
 // Program:        Common Evaluation Platform (CEP)
 // Description:    aes wrapper with LLKI supports
 // Notes:          
 //************************************************************************
-
+`timescale 1ns/1ns
 //
 // AES with LLKI wrapper
 //

unit_simulation/des3_sim/Makefile

@@ -1,5 +1,6 @@
 #//************************************************************************
 #// Copyright (C) 2020 Massachusetts Institute of Technology
+#// SPDX License Identifier: MIT
 #//
 #// File Name:      Makefile     
 #// Program:        Common Evaluation Platform (CEP)
@@ -16,6 +17,17 @@ LLKI_EN      = 1
 USE_MOCK_LLKI   = 1
 CORE_WITH_LLKI = real_des3_with_llki
 #
+# Add Cadence supports ro tun on RHEL7 machine
+#
+CADENCE  = 0
+ifeq (${CADENCE},1)
+DEFINE_LIST += +define+CADENCE
+export CADENCE_ENABLE_AVSREQ_63188_PHASE_1:=1
+export CADENCE_ENABLE_AVSREQ_44905_PHASE_1:=1
+# also might need to set  as sudo
+#sudo setsebool -P mmap_low_allowed 1
+endif
+#
 #
 #
 ifeq (${LLKI_EN},0)
@@ -44,14 +56,19 @@ DEFINE_LIST += +define+DUT_NAME=${DUT_NAME} +define+TB_NAME=${TB_NAME}
 #
 #
 all: des3_stimulus.txt
+ifeq (${CADENCE},1)
+	xrun -64 -sv +acc *.sv ${CORE_VFILES} ${LLKI_FILES} ${DEFINE_LIST} -y ../llki_supports +libext+.v +libext+.sv +incdir+../llki_supports -xlm_bq1
+else
 	vlog -64 -sv +acc *.sv ${CORE_VFILES} ${LLKI_FILES} ${DEFINE_LIST} -y ../llki_supports +libext+.v +libext+.sv +incdir+../llki_supports
 	vopt -64 +nolibcell +nospecify +notimingchecks ${TB_NAME} -o ${TB_NAME}_opt
 	vsim -64 ${TB_NAME}_opt -batch -do vsim.do -logfile ${TB_NAME}.log -wlf ${TB_NAME}.wlf
+endif
 
 des3_stimulus.txt : des3_stimulus.txt.gz
 	gunzip -c $< > $@
 
 clean:
 	rm -rf work *.wlf *.log *.txt
+	rm -rf xcelium.d
 
 

unit_simulation/des3_sim/des3_mock_tss.sv

@@ -1,12 +1,13 @@
 //************************************************************************
 /// Copyright (C) 2020 Massachusetts Institute of Technology
+// SPDX License Identifier: MIT
 //
 // File Name:      des3_mock_tss.sv
 // Program:        Common Evaluation Platform (CEP)
 // Description:    des3 wrapper with LLKI supports
 // Notes:          
 //************************************************************************
-
+`timescale 1ns/1ns
 //
 // DES with LLKI wrapper
 //

unit_simulation/dft_sim/Makefile

@@ -1,5 +1,6 @@
 #//************************************************************************
 #// Copyright (C) 2020 Massachusetts Institute of Technology
+#// SPDX License Identifier: MIT
 #//
 #// File Name:      Makefile     
 #// Program:        Common Evaluation Platform (CEP)
@@ -15,6 +16,18 @@ LLKI_EN      = 1
 #
 USE_MOCK_LLKI   = 1
 CORE_WITH_LLKI = real_dft_with_llki
+#
+# Add Cadence supports ro tun on RHEL7 machine
+#
+CADENCE  = 0
+ifeq (${CADENCE},1)
+DEFINE_LIST += +define+CADENCE
+export CADENCE_ENABLE_AVSREQ_63188_PHASE_1:=1
+export CADENCE_ENABLE_AVSREQ_44905_PHASE_1:=1
+# also might need to set  as sudo
+#sudo setsebool -P mmap_low_allowed 1
+endif
+
 #
 #
 #
@@ -42,14 +55,19 @@ DEFINE_LIST += +define+DUT_NAME=${DUT_NAME} +define+TB_NAME=${TB_NAME}
 #
 #
 all: dft_stimulus.txt
+ifeq (${CADENCE},1)
+	xrun -64 -sv +acc dft_top_mock_tss.sv dft_tb.sv ${CORE_VFILES} ${LLKI_FILES} ${DEFINE_LIST} -y ../llki_supports +libext+.v +libext+.sv +incdir+../llki_supports -xlm_bq1
+else
 	vlog -64 -sv +acc *.sv ${CORE_VFILES} ${LLKI_FILES} ${DEFINE_LIST} -y ../llki_supports +libext+.v +libext+.sv +incdir+../llki_supports
 	vopt -64 +nolibcell +nospecify +notimingchecks ${TB_NAME} -o ${TB_NAME}_opt
 	vsim -64 ${TB_NAME}_opt -batch -do vsim.do -logfile ${TB_NAME}.log -wlf ${TB_NAME}.wlf
+endif
 
 dft_stimulus.txt : dft_stimulus.txt.gz
 	gunzip -c $< > $@
 
 clean:
 	rm -rf work *.wlf *.log *.txt
+	rm -rf xcelium.d
 
 

unit_simulation/dft_sim/dft_top_mock_tss.sv

@@ -1,12 +1,13 @@
 //************************************************************************
 // Copyright (C) 2020 Massachusetts Institute of Technology
+// SPDX License Identifier: MIT
 //
 // File Name:      dft_top_mock_tss.sv
 // Program:        Common Evaluation Platform (CEP)
 // Description:    dft_top wrapper with LLKI supports
 // Notes:          
 //************************************************************************
-
+`timescale 1ns/1ns
 
 //
 // DFT with LLKI wrapper

unit_simulation/fir_sim/FIR_filter_mock_tss.sv

@@ -1,11 +1,13 @@
 //************************************************************************
 // Copyright (C) 2020 Massachusetts Institute of Technology
+// SPDX License Identifier: MIT
 //
 // File Name:      FIR_filter_mock_tss.sv
 // Program:        Common Evaluation Platform (CEP)
 // Description:    FIR_filter wrapper with LLKI supports
 // Notes:          
 //************************************************************************
+`timescale 1ns/1ns
 
 
 //

unit_simulation/fir_sim/Makefile

@@ -1,5 +1,6 @@
 #//************************************************************************
 #// Copyright (C) 2020 Massachusetts Institute of Technology
+#// SPDX License Identifier: MIT
 #//
 #// File Name:      Makefile     
 #// Program:        Common Evaluation Platform (CEP)
@@ -16,6 +17,17 @@ LLKI_EN      = 1
 USE_MOCK_LLKI   = 1
 CORE_WITH_LLKI = real_FIR_with_llki
 #
+# Add Cadence supports ro tun on RHEL7 machine
+#
+CADENCE  = 0
+ifeq (${CADENCE},1)
+DEFINE_LIST += +define+CADENCE
+export CADENCE_ENABLE_AVSREQ_63188_PHASE_1:=1
+export CADENCE_ENABLE_AVSREQ_44905_PHASE_1:=1
+# also might need to set  as sudo
+#sudo setsebool -P mmap_low_allowed 1
+endif
+#
 #
 #
 
@@ -41,14 +53,19 @@ DEFINE_LIST += +define+DUT_NAME=${DUT_NAME} +define+TB_NAME=${TB_NAME}
 #
 #
 all: fir_stimulus.txt
+ifeq (${CADENCE},1)
+	xrun -64 -sv +acc *.sv ${CORE_VFILES} ${LLKI_FILES} ${DEFINE_LIST} -y ../llki_supports +libext+.v +libext+.sv +incdir+../llki_supports -xlm_bq1
+else
 	vlog -64 -sv +acc *.sv ${CORE_VFILES} ${LLKI_FILES} ${DEFINE_LIST} -y ../llki_supports +libext+.v +libext+.sv +incdir+../llki_supports
 	vopt -64 +nolibcell +nospecify +notimingchecks ${TB_NAME} -o ${TB_NAME}_opt
 	vsim -64 ${TB_NAME}_opt -batch -do vsim.do -logfile ${TB_NAME}.log -wlf ${TB_NAME}.wlf
+endif
 
 fir_stimulus.txt : fir_stimulus.txt.gz
 	gunzip -c $< > $@
 
 clean:
 	rm -rf work *.wlf *.log *.txt
+	rm -rf xcelium.d