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CEP Release v2.3
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Fiscarelli committed Apr 9, 2020
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15 changes: 9 additions & 6 deletions README.md
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Expand Up @@ -4,7 +4,7 @@
<img src="./cep_logo.jpg">
</p>
<p align="center">
v2.2
v2.3
<br>
Copyright 2020 Massachusetts Institute of Technology
</p>
Expand All @@ -15,7 +15,7 @@ The Common Evaluation Platform (CEP) is intended as a surrogate System on a Chip

Additional information on the objectives of the CEP may be found in [./CEP_SecEvalTargets.pdf](CEP_SecEvalTargets.pdf).

CEP v2.2 is based on the SiFive U500 Platform which leverages the UCB Rocket Chip. Much of the design is described in Chisel (https://github.com/freechipsproject/chisel3), a domain specific extension to Scala tailored towards constructing hardware. The output of the Chisel generators is synthesizable verilog.
The CEP is based on the SiFive U500 Platform which leverages the UCB Rocket Chip. Much of the design is described in Chisel (https://github.com/freechipsproject/chisel3), a domain specific extension to Scala tailored towards constructing hardware. The output of the Chisel generators is synthesizable verilog.

Currently, the test platform for the CEP is the Xilinx VC-707 FPGA Development Board. Longer term plans include migrating to other platforms with the eventual goal of taping out an ASIC.

Expand All @@ -32,7 +32,7 @@ Currently, the test platform for the CEP is the Xilinx VC-707 FPGA Development B


## Pre-requisites (validated test/build configuration):
The following items describe the configuration of the system that CEP v2.2 has been developed and tested on:
The following items describe the configuration of the system that CEP has been developed and tested on:
* Ubuntu 16.04 LTS x86_64
* Modelsim Questa Sim-64 v2019.1 (for co-simulation)
* Xilinx Vivado 2018.3 (Design or System Edition)
Expand Down Expand Up @@ -168,7 +168,7 @@ Configure your VC-707 with the following DIP switch settings (SW11):
These steps assume prerequisites have been installed and all external dependencies have been fetched.
There are two primary build steps for CEP v2.2, the hardware and the software.
There are two primary build steps for the CEP, the hardware and the software.
### Building the Hardware
Expand Down Expand Up @@ -234,7 +234,7 @@ You should see the following logo/text appear:
./+++++++++++oo+++: +oo++o++++o+o+oo+oo.- `s+++s`-
.--:---:-:-::-::` -::::::::::::::::::. :::::.
Common Evaluation Platform v2.2
Common Evaluation Platform v2.3
Copyright 2019 Massachusetts Institute of Technology
Built upon the SiFive Freedom U500 Platform using
Expand Down Expand Up @@ -262,7 +262,7 @@ At the command prompt, you can run the CEP diagnostics by commanding `cep_diag`.
A partial output should be similar to:

```sh
*** CEP Tag=CEPTest CEP HW VERSION = v2.2 was built on Dec 17 2019*
*** CEP Tag=CEPTest CEP HW VERSION = v2.3 was built on Dec 17 2019*
CEP FPGA Physical=0x70000000 -> Virtual=0x000000200034d000
gSkipInit=0/0
gverbose=0/0
Expand Down Expand Up @@ -353,6 +353,9 @@ v2.1 - (31 October 2019)
v2.2 - (31 January 2020)
* Added co-simulation environment that supports both Bus Functional Model (BFM) and Baremetal simulation modes. Additional diagnostic capabilities within Linux.

v2.3 - (17 April 2020)
* Added unit-level testbenches for all CEP cores. Co-simulation modified to generate unit-level test stimulus.

## Licensing
The CEP been developed with a goal of using components with non-viral, open source licensing whenever possible. When not feasible (such as Linux), pointers to reference repositories are given using the [get_external_dependencies.sh](./get_external_dependencies.sh) script.

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70 changes: 33 additions & 37 deletions cosim/README.md
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Expand Up @@ -110,45 +110,42 @@ At the Vivado's tcl console (bottom), type/cut/paste and execute the below comma

Replace /opt/questa-2019.1/questasim/bin and ./cosim/xil_lib above with appropriate paths of your setup

```
## How to run test(s): ##
# How to run test(s): #

NOTE: type "make usage" for help.

* Run a test interactively: (use regTest as example)

```
cd <CEP_ROOT>/cosim/bfmTests/regTest
cd .../cosim/bfmTests/regTest
make
```

* Run full regression:

```
<CEP_ROOT>/cosim
make <-- this will run all tests in both BFM and bare metal
```
cd .../cosim
make <-- this will run all tests in both BFM and bare metal
```

or

```
cd <CEP_ROOT>/cosim/bfmTests
make <-- this will run all tests under BFM mode only
cd .../cosim/bfmTests
make <-- this will run all tests under BFM mode only
```

or

```
cd <CEP_ROOT>/cosim/bareMetalTests
make <-- this will run all tests under bare metal mode only
cd .../cosim/bareMetalTests
make <-- this will run all tests under bare metal mode only
```

* How to check regression results (assuming tests have been run):
* How to check regression results:

```
cd <CEP_ROOT>/cosim
cd .../cosim
make summary
```
it should give you something like this:
Expand All @@ -162,33 +159,32 @@ PASS : /home/aduong/CEP/CEP-master/cosim/bareMetalTests/ddr3 (NEW SEED)
PASS : /home/aduong/CEP/CEP-master/cosim/bareMetalTests/printfTest (NEW SEED)
PASS : /home/aduong/CEP/CEP-master/cosim/bareMetalTests/regression (NEW SEED)
```

## How to add new test: ##
# How to add new test: #

First pick which test category the new test should be under: bfmTests or bareMetalTests or <others_yet_created>

cd <bfmTests_or_bareMetalTests_or_others>
cp -rp ddr3Test <your_new_test> <-- cut/paste any existing test as reference to your new test
cd <your_new_test>
ls (should have the list of file shown below)
c_dispatch.h <-- make sure all the header files and Makefile are there and don't need to touch any of these
c_module.h
Makefile
testHostory.txt <-- history of PASS/FAIL and random seeds used for this particular test from day of creation.
c_dispatch.cc <-- top dispatch to control how many cores to run
c_module.cc <-- the test wrapper to run under each core
Note:
in BFM mode, this is the test wrapper that calls your new test
in Bare Metal mode, don't need to touch. See riscv_wrapper.cc
riscv_wrapper.cc <-- This is the test wrapper that calls your new test in Bare Metal Mode only.
Note: under BFM category, this file is not needed.
cd <bfmTests_or_bareMetalTests_or_others>
cp -rp ddr3Test <your_new_test> <-- cut/paste any existing test as reference to your new test


cd <your_new_test>
ls (should have the list of file shown below)

c_dispatch.h <-- make sure all the header files and Makefile are there and don't need to touch any of these
c_module.h
Makefile
testHostory.txt <-- history of PASS/FAIL and random seeds used for this particular test from day of creation.
c_dispatch.cc <-- top dispatch to control how many cores to run
c_module.cc <-- the test wrapper to run under each core
Note:
in BFM mode, this is the test wrapper that calls your new test
in Bare Metal mode, don't need to touch. See riscv_wrapper.cc
riscv_wrapper.cc <-- This is the test wrapper that calls your new test in Bare Metal Mode only.
Note: under BFM category, this file is not needed.

Let dig in further to each of these files:

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30 changes: 30 additions & 0 deletions cosim/bfmTests/aes/Makefile
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#//************************************************************************
#// Copyright (C) 2020 Massachusetts Institute of Technology
#//
#// File Name:
#// Program: Common Evaluation Platform (CEP)
#// Description:
#// Notes:
#//
#//************************************************************************
#
#
#
COSIM_NAME = $(shell cd ../..; basename `pwd`)
DUT_TOP_DIR = $(shell cd ../../..; pwd | ./${COSIM_NAME}/bin/strip_net.pl )
BLD_DIR = $(shell cd ..; pwd | ../bin/strip_net.pl )
TEST_SUITE = $(shell basename ${BLD_DIR})
TEST_DIR = $(shell cd .; pwd | ../../bin/strip_net.pl )
TEST_NAME = $(shell basename `pwd`)
SIM_DIR = ${DUT_TOP_DIR}/${COSIM_NAME}

#
# Top target!!!
#
all: .vrun_flag

#
# override anything here before calling the common file
#
include ${BLD_DIR}/common.make

104 changes: 104 additions & 0 deletions cosim/bfmTests/aes/c_dispatch.cc
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//************************************************************************
// Copyright (C) 2020 Massachusetts Institute of Technology
//
// File Name:
// Program: Common Evaluation Platform (CEP)
// Description:
// Notes:
//
//************************************************************************
#include <unistd.h>
#include "v2c_cmds.h"
#include "access.h"
#include "c_dispatch.h"
#include "c_module.h"
#include "cep_apis.h"
#include "cep_adrMap.h"
#include "simPio.h"
/*
* main
*/
int main(int argc, char *argv[])
{

/* ===================================== */
/* SETUP SECTION FOR SIMULATION */
/* ===================================== */
unsigned long seed;
sscanf(argv[1],"0x%x",&seed);
printf("Seed = 0x%x\n",seed);
int errCnt = 0;
int verbose = 0x1f;

/* ===================================== */
/* spawn all the paralle threads */
/* ===================================== */
int activeSlot=0; // only 1 board
//
// ============================
// fork all the tests here
// ============================
//
shPthread thr;
//
// max number of cores not include the system thread
//
int maxHost = MAX_CORES; // number of cores/threads
//
// each bit is to turn on the given core (bit0 = core0, bit1=core1, etc..)
//
long unsigned int mask = 1 << (seed & 0x3);
//
// Set the active CPU mask before spawn the threads...
//
thr.SetActiveMask(mask);
//
// c_module is the threead to run
//
for (int i=0;i<maxHost;i++) {
if ((long unsigned int)(1 << i) & mask) {
thr.ForkAThread(activeSlot,i,verbose, seed * (1+i), c_module);
}
}
//
// lastly: Added system thread always
//
thr.AddSysThread(SYSTEM_SLOT_ID,SYSTEM_CPU_ID);
//
// Enable vector capture-ing
DUT_WRITE_DVT(DVTF_AES_CAPTURE_EN_BIT,DVTF_AES_CAPTURE_EN_BIT,1);
// ============================
// Turn on the wave here
// ============================
//
int cycle2start=0;
int cycle2capture=-1; // til end
int wave_enable=1;
#ifndef NOWAVE
dump_wave(cycle2start, cycle2capture, wave_enable);
#endif
//
// ============================
// wait until all the threads are done
// ============================
//
int Done = 0;
while (!Done) {
Done = thr.AllThreadDone();
sleep(2);
}
/* ===================================== */
/* END-OF-TEST CHECKING */
/* ===================================== */
errCnt += thr.GetErrorCount();
if (errCnt != 0) {
LOGE("======== TEST FAIL ========== %x\n",errCnt);
} else {
LOGI("%s ======== TEST PASS ========== \n",__FUNCTION__);
}
//
// shutdown HW side
//
thr.Shutdown();
return(errCnt);
}
22 changes: 22 additions & 0 deletions cosim/bfmTests/aes/c_dispatch.h
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//************************************************************************
// Copyright (C) 2020 Massachusetts Institute of Technology
//
// File Name:
// Program: Common Evaluation Platform (CEP)
// Description:
// Notes:
//
//************************************************************************
#ifndef __C_DISPATCH_H
#define __C_DISPATCH_H


// Dispatch setup
#ifdef LONGTEST
#define MAX_LOOP 50
#else
#define MAX_LOOP 5
#endif

#endif

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