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@merledu

Micro Electronics Research Laboratory

A non-profit organization fostering research on IoT, AI, and ML-based architectures leveraging the open-source RISC-V ISA.

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  1. OpenTCAM OpenTCAM Public

    An open-source Ternary Content Addressable Memory (TCAM) compiler.

    Python 20 11

  2. azadi-soc azadi-soc Public

    Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.

    SystemVerilog 26 10

  3. Google-Summer-of-Code Google-Summer-of-Code Public

    Project ideas list for Google Summer of Code.

    11 2

  4. Ibtida Ibtida Public

    A basic System on a Chip (SoC) based on the Buraq core for the Internet of Things (IoT).

    Verilog 4 2

  5. TileLink TileLink Public

    TileLink Uncached Lightweight (TL-UL) implementation on Chisel.

    Scala 21 10

  6. buraq_mini buraq_mini Public

    This repository contains the 5 stage pipelined CPU implemented on the RISC-V ISA and Chisel hardware construction language (HDL)

    Scala 8 6

Repositories

Showing 10 of 137 repositories
  • Athestia Public

    Clean slate application using NDN with Dilithium to enhance security in future internet technology

    merledu/Athestia’s past year of commit activity
    2 0 0 0 Updated Nov 13, 2024
  • KyberQuanta Public

    A Kyber768-90's Hardware Accelerator.

    merledu/KyberQuanta’s past year of commit activity
    Python 3 2 0 0 Updated Nov 12, 2024
  • oxygen Public

    A RISC-V Simulator

    merledu/oxygen’s past year of commit activity
    Python 2 GPL-3.0 3 0 1 Updated Nov 11, 2024
  • vaquita Public
    merledu/vaquita’s past year of commit activity
    Scala 12 GPL-3.0 6 0 1 Updated Nov 6, 2024
  • CryptoCortex Public
    merledu/CryptoCortex’s past year of commit activity
    Jupyter Notebook 0 1 0 0 Updated Oct 27, 2024
  • SoC-Now-Generator Public

    An open source Mini SoC Generator which will generate SoC based on parameters.

    merledu/SoC-Now-Generator’s past year of commit activity
    Verilog 1 1 8 0 Updated Oct 3, 2024
  • jigsaw Public

    A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).

    merledu/jigsaw’s past year of commit activity
    Scala 3 7 1 2 Updated Oct 3, 2024
  • caravan Public

    A caravan equipped with API for creating bus protocols in Chisel with ease.

    merledu/caravan’s past year of commit activity
    Scala 13 Apache-2.0 11 4 0 Updated Oct 3, 2024
  • soc-studio Public
    merledu/soc-studio’s past year of commit activity
    0 0 0 0 Updated Oct 2, 2024
  • nucleusrv Public

    NucleusRV - A 32-bit 5 staged pipelined risc-v core.

    merledu/nucleusrv’s past year of commit activity
    C 60 GPL-3.0 24 15 0 Updated Oct 1, 2024
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