Implement INC opcodes

maxfierke · Dec 20, 2023 · a59e715 · a59e715
1 parent e3d18bd
commit a59e715
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Showing 2 changed files with 130 additions and 0 deletions.
diff --git a/cpu/cpu.go b/cpu/cpu.go
@@ -55,18 +55,57 @@ func (cpu *CPU) Execute(mmu *mem.MMU, inst *isa.Instruction) (nextPC uint16, cyc
 	switch opcode.Addr {
 	case 0x00:
 		// NOP
+	case 0x03:
+		// INC BC
+		cpu.Reg.BC.Inc(1)
+	case 0x04:
+		// INC B
+		cpu.inc8(cpu.Reg.B)
 	case 0x09:
 		// ADD HL, BC
 		cpu.add16(cpu.Reg.HL, cpu.Reg.BC.Read())
+	case 0x0C:
+		// INC C
+		cpu.inc8(cpu.Reg.C)
+	case 0x13:
+		// INC DE
+		cpu.Reg.DE.Inc(1)
+	case 0x14:
+		// INC D
+		cpu.inc8(cpu.Reg.D)
 	case 0x19:
 		// ADD HL, DE
 		cpu.add16(cpu.Reg.HL, cpu.Reg.DE.Read())
+	case 0x1C:
+		// INC E
+		cpu.inc8(cpu.Reg.E)
+	case 0x23:
+		// INC HL
+		cpu.Reg.HL.Inc(1)
+	case 0x24:
+		// INC H
+		cpu.inc8(cpu.Reg.H)
 	case 0x29:
 		// ADD HL, HL
 		cpu.add16(cpu.Reg.HL, cpu.Reg.HL.Read())
+	case 0x2C:
+		// INC L
+		cpu.inc8(cpu.Reg.L)
+	case 0x33:
+		// INC SP
+		cpu.SP.Inc(1)
+	case 0x34:
+		// INC (HL)
+		value := mmu.Read8(cpu.Reg.HL.Read())
+		fauxReg := &Register[uint8]{name: "(HL)", value: value}
+		cpu.add8(fauxReg, 1)
+		mmu.Write8(cpu.Reg.HL.Read(), fauxReg.Read())
 	case 0x39:
 		// ADD HL, SP
 		cpu.add16(cpu.Reg.HL, cpu.SP.Read())
+	case 0x3C:
+		// INC A
+		cpu.inc8(cpu.Reg.A)
 	case 0x80:
 		// ADD A, B
 		cpu.add8(cpu.Reg.A, cpu.Reg.B.Read())
@@ -216,6 +255,18 @@ func (cpu *CPU) add8(reg RWByte, value uint8) uint8 {
 	return newValue
 }
 
+func (cpu *CPU) inc8(reg RWByte) uint8 {
+	oldValue := reg.Read()
+	newValue := oldValue + 1
+	reg.Write(newValue)
+
+	cpu.Reg.F.Zero = newValue == 0
+	cpu.Reg.F.Subtract = false
+	cpu.Reg.F.HalfCarry = isHalfCarry8(oldValue, 1)
+
+	return newValue
+}
+
 func (cpu *CPU) add16(reg RWTwoByte, value uint16) uint16 {
 	newValue := reg.Read() + value
 	reg.Write(newValue)

diff --git a/cpu/cpu_test.go b/cpu/cpu_test.go
@@ -122,6 +122,85 @@ func TestExecuteAdd16TargetDECarry(t *testing.T) {
 	assertFlags(t, cpu, false, false, true, true)
 }
 
+func TestExecuteInc8(t *testing.T) {
+	cpu, _ := NewCPU()
+	inst, _ := cpu.opcodes.InstructionFromByte(cpu.PC.Read(), 0x3C, false)
+
+	cpu.Reg.A.Write(0x7)
+
+	cpu.Execute(NULL_MMU, inst)
+
+	assertRegEquals(t, cpu.Reg.A.Read(), 0x8)
+	assertFlags(t, cpu, false, false, false, false)
+}
+
+func TestExecuteInc8HalfCarry(t *testing.T) {
+	cpu, _ := NewCPU()
+	inst, _ := cpu.opcodes.InstructionFromByte(cpu.PC.Read(), 0x3C, false)
+
+	cpu.Reg.A.Write(0xF)
+
+	cpu.Execute(NULL_MMU, inst)
+
+	assertRegEquals(t, cpu.Reg.A.Read(), 0x10)
+	assertFlags(t, cpu, false, false, true, false)
+}
+
+func TestExecuteInc8Overflow(t *testing.T) {
+	cpu, _ := NewCPU()
+	inst, _ := cpu.opcodes.InstructionFromByte(cpu.PC.Read(), 0x3C, false)
+
+	cpu.Reg.A.Write(0xFF)
+
+	cpu.Execute(NULL_MMU, inst)
+
+	assertRegEquals(t, cpu.Reg.A.Read(), 0x00)
+	assertFlags(t, cpu, true, false, true, false)
+}
+
+func TestExecuteInc16ByteOverflow(t *testing.T) {
+	cpu, _ := NewCPU()
+	inst, _ := cpu.opcodes.InstructionFromByte(cpu.PC.Read(), 0x03, false)
+
+	cpu.Reg.BC.Write(0xFF)
+
+	cpu.Execute(NULL_MMU, inst)
+
+	assertRegEquals(t, cpu.Reg.BC.Read(), 0x100)
+	assertRegEquals(t, cpu.Reg.B.Read(), 0x1)
+	assertRegEquals(t, cpu.Reg.C.Read(), 0x0)
+	assertFlags(t, cpu, false, false, false, false)
+}
+
+func TestExecuteInc16Overflow(t *testing.T) {
+	cpu, _ := NewCPU()
+	inst, _ := cpu.opcodes.InstructionFromByte(cpu.PC.Read(), 0x03, false)
+
+	cpu.Reg.BC.Write(0xFFFF)
+
+	cpu.Execute(NULL_MMU, inst)
+
+	assertRegEquals(t, cpu.Reg.BC.Read(), 0x0)
+	assertRegEquals(t, cpu.Reg.B.Read(), 0x0)
+	assertRegEquals(t, cpu.Reg.C.Read(), 0x0)
+	assertFlags(t, cpu, false, false, false, false)
+}
+
+func TestExecuteIncHLIndirect(t *testing.T) {
+	cpu, _ := NewCPU()
+	ram := make([]byte, 0xFFFF)
+	mmu := mem.NewMMU(ram)
+
+	cpu.Reg.HL.Write(0xFFF8)
+	mmu.Write8(0xFFF8, 0x03)
+
+	inst, _ := cpu.opcodes.InstructionFromByte(cpu.PC.Read(), 0x34, false)
+
+	cpu.Execute(mmu, inst)
+
+	assertRegEquals(t, ram[0xFFF8], 0x04)
+}
+
 func TestExecuteJump(t *testing.T) {
 	cpu, _ := NewCPU()
 	ram := make([]byte, 0xFFFF)