Discern between devices with CPU AGB 0/A/A E and CPU AGB B/B E revisions

README.md

@@ -20,10 +20,15 @@ Currently it cannot discern between all SoC revisions. Devices will be reported
 - CPU CGB C
 - CPU CGB D
 - CPU CGB E
-- CPU AGB ?
+- CPU AGB 0/A/A E
+- CPU AGB B/B E
 
 ## Release Notes
 
+v0.3
+
+- Use VRAM reads at the transition from PPU mode 3 to mode 0 discern between devices with CPU AGB 0/A/A E (AGB and GB Player) and CPU AGB B/B E (AGS) revisions
+
 v0.2.2
 
 - Discern between CPU CGB 0/A/B/C, CPU CGB D, and CPU CGB E revisions using more simple "extra OAM" test

src/which.asm

@@ -66,9 +66,7 @@ main::
     call ResetCursor
     call LoadFont
 
-    lcd_on
-
-    print_string_literal "which.gb v0.2.2\\n---------------\\n\\nseems to be a...\\n\\n"
+    print_string_literal "which.gb v0.3\\n-------------\\n\\nseems to be a...\\n\\n"
 
     ld a, [wInitialA]
     cp $01
@@ -78,7 +76,7 @@ main::
     jp z, is_mgb_or_sgb2
 
     cp $11
-    jp z, is_cgb_or_agb
+    jp z, is_cgb_or_agb_or_ags
 
     print_string_literal "Unknown!"
     jp done
@@ -123,14 +121,10 @@ is_mgb::
 
 
 
-is_cgb_or_agb::
+is_cgb_or_agb_or_ags::
     ld a, [wInitialB]
     cp $00
-    jr z, is_cgb
-
-is_agb::
-    print_string_literal "CPU AGB ?"
-    jp done    
+    jp nz, is_agb_or_ags
 
 is_cgb::
     ; wave ram is not initialised on cgb0
@@ -204,8 +198,25 @@ is_cgb0::
     jp done    
 
 
-done:
-    jr done
+is_agb_or_ags::
+    call check_agb_or_ags
+    cp $22
+    jr z, is_ags
+
+is_agb::
+    print_string_literal "CPU AGB 0/A/A E"
+    jp done
+
+is_ags::
+    print_string_literal "CPU AGB B/B E"
+    jp done
+
+
+done::
+    lcd_on
+
+.forever:
+    jr .forever
 
 
 
@@ -252,3 +263,59 @@ check_cgb_ab_or_c::
     ld a, [hl]
 
     ret
+
+
+; Check how VRAM reads behave at the transition from mode 3 to mode 0.
+; Assumes LCD is off, and leaves LCD on afterwards.
+; 
+; @return a `$11` on AGB devices, or `$22` on AGS devices
+check_agb_or_ags::
+    ; fill tile data from $8000-8fff with alternating $11 and $22 values
+    ld hl, $8000
+    ld bc, $1000 / 2
+.tile_data_loop:
+    ld a, $11
+    ld [hl+], a
+    ld a, $22
+    ld [hl+], a
+    dec bc
+    ld a, b
+    or c
+    jr nz, .tile_data_loop
+
+    ; fill first row of tile map with $00
+    xor a
+    ld hl, $9c00
+    ld bc, 32
+    call MemSetSmall
+
+    ; configure ppu registers
+    bg_map_9c00
+    bg_tile_data_8800
+    xor a
+    ldh [rSCY], a
+    ld a, 3
+    ldh [rSCX], a   ; SCX must be 3 to get the correct timing
+
+    ; turn on the lcd
+    ld hl, rLCDC
+    set 7, [hl]
+
+    ld hl, $8000
+    delay 172
+
+    ; first read is $00
+    ld a, [hl]
+
+    ; second read is $11 or $22
+    delay 114 - 2
+    ld a, [hl]
+
+    ; reset registers to original values
+    push af
+    bg_map_9800
+    xor a
+    ldh [rSCX], a
+    pop af
+
+    ret