This repository contains the design of RISC-V CPU 5-staged Core

VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.

HDLBits website practices & solutions

This repository is intended for the documentation of all learning outcomes and processes of VSDSquadron RISCV internship.

Verilog AXI components for FPGA implementation

The Repository contains the code of various Digital Circuits

System-Verilog

100 Days of RTL

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edg…

Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools

100 Days of RTL

UART implementation using verilog

Implementation of 32-bit MIPS-processor using SystemVerilog HDL

Advanced Encryption Standard (AES) modelling, using Verilog HDL.

This is the collection of Schematics of various digital electronics elements, verilog codes and test benches of different operation and circuits

Hardware Schematic of Four Bit Signed Calculator designed using Xilinx ISE 14.7

This is AR/VR based project made for NASA SPACE APP CHALLENGE 2021

Submission repo for Coderspree

Submission repo for Coderspree