This project is aimed at creating a minimal HEVC encoder that can run on a mid-range FPGA device.
The features that will be supported
- Intra only
- CTU：32x32 (or 16x16)
- CU： 4x4 8x8 ( 16x16 maybe）
- TU ： 4x4 8x8
- All intra prediction mode support
- CABAC
-
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lulinchen/TinyHEVC
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A tiny hardware HEVC/H.265 encoder
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