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Relative paths in run_modelsim.py and other changes to make Modelsim work on non-Utah machines #247
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8a026f7
fixing modelsim.py to use relative paths
nachiket f10fc2b
fixing modelsim.py to use relative paths
nachiket adc31c6
fixing modelsim.py to use relative paths
nachiket 63e06db
fixing modelsim.py to use relative paths and various other paths
nachiket 0492629
Merge branch 'master' of github.com:watcag/OpenFPGA
60754bf
adding k6_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
bf02248
what is going no
nachiket 86bd58c
what is going no
nachiket 12d8282
some typos in XML fixed
nachiket 2bb069f
so much weirdness
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206 changes: 206 additions & 0 deletions
206
openfpga_flow/openfpga_arch/k6_N10_stdcell_mux_40nm_openfpga_synthesizable.xml
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,206 @@ | ||
| <!-- Architecture annotation for OpenFPGA framework | ||
| This annotation supports the k6_N10_40nm.xml | ||
| - General purpose logic block | ||
| - K = 6, N = 10, I = 40 | ||
| - Single mode | ||
| - Routing architecture | ||
| - L = 4, fc_in = 0.15, fc_out = 0.1 | ||
| --> | ||
| <openfpga_architecture> | ||
| <technology_library> | ||
| <device_library> | ||
| <device_model name="logic" type="transistor"> | ||
| <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/> | ||
| <design vdd="0.9" pn_ratio="2"/> | ||
| <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/> | ||
| <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/> | ||
| </device_model> | ||
| <device_model name="io" type="transistor"> | ||
| <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/> | ||
| <design vdd="2.5" pn_ratio="3"/> | ||
| <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/> | ||
| <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/> | ||
| </device_model> | ||
| </device_library> | ||
| <variation_library> | ||
| <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/> | ||
| <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/> | ||
| </variation_library> | ||
| </technology_library> | ||
| <circuit_library> | ||
| <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/inv.v"> | ||
| <design_technology type="cmos" topology="inverter" size="1"/> | ||
| <device_technology device_model_name="logic"/> | ||
| <port type="input" prefix="in" size="1"/> | ||
| <port type="output" prefix="out" size="1"/> | ||
| <delay_matrix type="rise" in_port="in" out_port="out"> | ||
| 10e-12 | ||
| </delay_matrix> | ||
| <delay_matrix type="fall" in_port="in" out_port="out"> | ||
| 10e-12 | ||
| </delay_matrix> | ||
| </circuit_model> | ||
| <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/buf4.v"> | ||
| <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/> | ||
| <device_technology device_model_name="logic"/> | ||
| <port type="input" prefix="in" size="1"/> | ||
| <port type="output" prefix="out" size="1"/> | ||
| <delay_matrix type="rise" in_port="in" out_port="out"> | ||
| 10e-12 | ||
| </delay_matrix> | ||
| <delay_matrix type="fall" in_port="in" out_port="out"> | ||
| 10e-12 | ||
| </delay_matrix> | ||
| </circuit_model> | ||
| <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/tap_buf4.v"> | ||
| <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/> | ||
| <device_technology device_model_name="logic"/> | ||
| <port type="input" prefix="in" size="1"/> | ||
| <port type="output" prefix="out" size="1"/> | ||
| <delay_matrix type="rise" in_port="in" out_port="out"> | ||
| 10e-12 | ||
| </delay_matrix> | ||
| <delay_matrix type="fall" in_port="in" out_port="out"> | ||
| 10e-12 | ||
| </delay_matrix> | ||
| </circuit_model> | ||
| <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true"> | ||
| <design_technology type="cmos" topology="OR"/> | ||
| <device_technology device_model_name="logic"/> | ||
| <input_buffer exist="false"/> | ||
| <output_buffer exist="false"/> | ||
| <port type="input" prefix="a" size="1"/> | ||
| <port type="input" prefix="b" size="1"/> | ||
| <port type="output" prefix="out" size="1"/> | ||
| <delay_matrix type="rise" in_port="a b" out_port="out"> | ||
| 10e-12 5e-12 | ||
| </delay_matrix> | ||
| <delay_matrix type="fall" in_port="a b" out_port="out"> | ||
| 10e-12 5e-12 | ||
| </delay_matrix> | ||
| </circuit_model> | ||
| <!-- Define a circuit model for the standard cell MUX2 | ||
| OpenFPGA requires the following truth table for the MUX2 | ||
| When the select signal sel is enabled, the first input, i.e., in0 | ||
| will be propagated to the output, i.e., out | ||
| If your standard cell provider does not offer the exact truth table, | ||
| you can simply swap the inputs as shown in the example below | ||
| --> | ||
| <circuit_model type="gate" name="MUX2" prefix="MUX2" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/mux2.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/mux2.v"> | ||
| <design_technology type="cmos" topology="MUX2"/> | ||
| <device_technology device_model_name="logic"/> | ||
| <input_buffer exist="false"/> | ||
| <output_buffer exist="false"/> | ||
| <port type="input" prefix="in0" lib_name="B" size="1"/> | ||
| <port type="input" prefix="in1" lib_name="A" size="1"/> | ||
| <port type="input" prefix="sel" lib_name="S0" size="1"/> | ||
| <port type="output" prefix="out" lib_name="Y" size="1"/> | ||
| </circuit_model> | ||
| <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true"> | ||
| <design_technology type="cmos"/> | ||
| <input_buffer exist="false"/> | ||
| <output_buffer exist="false"/> | ||
| <port type="input" prefix="in" size="1"/> | ||
| <port type="output" prefix="out" size="1"/> | ||
| <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE --> | ||
| </circuit_model> | ||
| <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true"> | ||
| <design_technology type="cmos"/> | ||
| <input_buffer exist="false"/> | ||
| <output_buffer exist="false"/> | ||
| <port type="input" prefix="in" size="1"/> | ||
| <port type="output" prefix="out" size="1"/> | ||
| <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined --> | ||
| </circuit_model> | ||
| <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true"> | ||
| <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> | ||
| <input_buffer exist="true" circuit_model_name="INVTX1"/> | ||
| <output_buffer exist="true" circuit_model_name="INVTX1"/> | ||
| <pass_gate_logic circuit_model_name="MUX2"/> | ||
| <port type="input" prefix="in" size="1"/> | ||
| <port type="output" prefix="out" size="1"/> | ||
| <port type="sram" prefix="sram" size="1"/> | ||
| </circuit_model> | ||
| <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true"> | ||
| <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> | ||
| <input_buffer exist="true" circuit_model_name="INVTX1"/> | ||
| <output_buffer exist="true" circuit_model_name="tap_buf4"/> | ||
| <pass_gate_logic circuit_model_name="MUX2"/> | ||
| <port type="input" prefix="in" size="1"/> | ||
| <port type="output" prefix="out" size="1"/> | ||
| <port type="sram" prefix="sram" size="1"/> | ||
| </circuit_model> | ||
| <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> --> | ||
| <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> | ||
| <design_technology type="cmos"/> | ||
| <input_buffer exist="true" circuit_model_name="INVTX1"/> | ||
| <output_buffer exist="true" circuit_model_name="INVTX1"/> | ||
| <port type="input" prefix="D" size="1"/> | ||
| <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/> | ||
| <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/> | ||
| <port type="output" prefix="Q" size="1"/> | ||
| <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" /> | ||
| </circuit_model> | ||
| <circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true"> | ||
| <design_technology type="cmos"/> | ||
| <input_buffer exist="true" circuit_model_name="INVTX1"/> | ||
| <output_buffer exist="true" circuit_model_name="INVTX1"/> | ||
| <lut_input_inverter exist="true" circuit_model_name="INVTX1"/> | ||
| <lut_input_buffer exist="true" circuit_model_name="buf4"/> | ||
| <pass_gate_logic circuit_model_name="MUX2"/> | ||
| <port type="input" prefix="in" size="6"/> | ||
| <port type="output" prefix="out" size="1"/> | ||
| <port type="sram" prefix="sram" size="64"/> | ||
| </circuit_model> | ||
| <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> --> | ||
| <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v"> | ||
| <design_technology type="cmos"/> | ||
| <input_buffer exist="true" circuit_model_name="INVTX1"/> | ||
| <output_buffer exist="true" circuit_model_name="INVTX1"/> | ||
| <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/> | ||
| <port type="input" prefix="D" size="1"/> | ||
| <port type="output" prefix="Q" size="1"/> | ||
| <port type="output" prefix="QN" size="1"/> | ||
| <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/> | ||
| </circuit_model> | ||
| <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v"> | ||
| <design_technology type="cmos"/> | ||
| <input_buffer exist="true" circuit_model_name="INVTX1"/> | ||
| <output_buffer exist="true" circuit_model_name="INVTX1"/> | ||
| <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/> | ||
| <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/> | ||
| <port type="input" prefix="outpad" lib_name="A" size="1"/> | ||
| <port type="output" prefix="inpad" lib_name="Y" size="1"/> | ||
| </circuit_model> | ||
| </circuit_library> | ||
| <configuration_protocol> | ||
| <organization type="scan_chain" circuit_model_name="DFFR"/> | ||
| </configuration_protocol> | ||
| <connection_block> | ||
| <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/> | ||
| </connection_block> | ||
| <switch_block> | ||
| <switch name="0" circuit_model_name="mux_tree_tapbuf"/> | ||
| </switch_block> | ||
| <routing_segment> | ||
| <segment name="L4" circuit_model_name="chan_segment"/> | ||
| </routing_segment> | ||
| <pb_type_annotations> | ||
| <!-- physical pb_type binding in complex block IO --> | ||
| <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/> | ||
| <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> | ||
| <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> | ||
| <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> | ||
| <!-- End physical pb_type binding in complex block IO --> | ||
|
|
||
| <!-- physical pb_type binding in complex block CLB --> | ||
| <!-- physical mode will be the default mode if not specified --> | ||
| <pb_type name="clb"> | ||
| <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model --> | ||
| <interconnect name="crossbar" circuit_model_name="mux_tree"/> | ||
| </pb_type> | ||
| <pb_type name="clb.fle[n1_lut6].ble6.lut6" circuit_model_name="lut6"/> | ||
| <pb_type name="clb.fle[n1_lut6].ble6.ff" circuit_model_name="DFFSRQ"/> | ||
| <!-- End physical pb_type binding in complex block IO --> | ||
| </pb_type_annotations> | ||
| </openfpga_architecture> |
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Submodule yosys
updated
2 files
| +53 −32 | techlibs/quicklogic/openfpga_arith_map.v | |
| +7 −40 | techlibs/quicklogic/openfpga_cells_sim.v |
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Can you avoid to modifying existing script templates? We can create a new template script with this feature.