Preserve escaped names

[alaindargelas]

Motivate of the pull request

• [ x] To address an existing issue. If so, please provide a link to the issue:
• Breaking new feature. If so, please describe details in the description part.

Describe the technical details

What is currently done? (Provide issue link if applicable)

When writing out the Verilog testbench, openfpga writes illegal Verilog of the port identifiers coming from Yosys were originally escaped names, ie $iopadmap$a .
Yosys creates those escaped names when using the iopad pass.

What does this pull request change?

Restore the escaped names when necessary.

Which part of the code base require a change

• VPR
• Tileable routing architecture generator
• [ X] OpenFPGA libraries
• FPGA-Verilog
• FPGA-Bitstream
• FPGA-SDC
• FPGA-SPICE
• Flow scripts
• Architecture library
• Cell library
• Documentation
• Regression tests
• Continous Integration (CI) scripts

Impact of the pull request

• Require a change on Quality of Results (QoR)
• Break back-compatibility. If so, please list who may be influenced.

[alaindargelas]

@tangxifan, @ganeshgore , please authorize my workflow run.

[alaindargelas]

@ganeshgore, @chungshien , how to run the code formatter for this repo?
There is no instructions I can find.

[chungshien-chai]

@ganeshgore, @chungshien , how to run the code formatter for this repo? There is no instructions I can find.

This is OpenFPGA repo right? You can do this "make format-all"