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115 changes: 56 additions & 59 deletions test/WaveOps/WaveActiveBallot.Wave32.test
Original file line number Diff line number Diff line change
@@ -1,59 +1,56 @@
#--- source.hlsl
RWStructuredBuffer<uint4> Out : register(u1);

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Github diff isn't great here. I think you are removing CRLF from this file but just want you to confirm.

I'm running your patch through sed and thats what seems to be going on.
curl -L https://patch-diff.githubusercontent.com/raw/llvm/offload-test-suite/pull/697.patch | sed -n 'l'

-# RUN: %offloader %t/pipeline.yaml %t.o\r$
+# RUN: %offloader %t/pipeline.yaml %t.o$

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Related: #741

[WaveSize(32)]
[numthreads(32, 1, 1)]
void main(uint3 threadID : SV_DispatchThreadID) {
// We expect the first resulting uint's bitmask to be
// 0xBFFFFFFF
Out[0] = WaveActiveBallot(threadID.x != 30);

// We expect the first resulting uint's bitmask to be
// 0x0000FFFF
Out[1] = WaveActiveBallot(threadID.x < 16);

// We expect the resulting uint4 to be 4 0x00000000's
Out[2] = WaveActiveBallot(false);
}

//--- pipeline.yaml

---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: Out
Format: UInt32
Stride: 4
FillSize: 48
- Name: ExpectedOut
Format: UInt32
Stride: 4
Data: [3221225471, 0, 0, 0, 65535, 0, 0, 0, 0, 0, 0, 0]
Results:
- Result: Test
Rule: BufferExact
Actual: Out
Expected: ExpectedOut
DescriptorSets:
- Resources:
- Name: Out
Kind: RWStructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
...
#--- end

# REQUIRES: WaveSize_32

# Bug: https://github.com/llvm/offload-test-suite/issues/688
# XFAIL: AMD && DirectX

# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
#--- source.hlsl
RWStructuredBuffer<uint4> Out : register(u1);

[WaveSize(32)]
[numthreads(32, 1, 1)]
void main(uint3 threadID : SV_DispatchThreadID) {
// We expect the first resulting uint's bitmask to be
// 0xBFFFFFFF
Out[0] = WaveActiveBallot(threadID.x != 30);

// We expect the first resulting uint's bitmask to be
// 0x0000FFFF
Out[1] = WaveActiveBallot(threadID.x < 16);

// We expect the resulting uint4 to be 4 0x00000000's
Out[2] = WaveActiveBallot(false);
}

//--- pipeline.yaml

---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: Out
Format: UInt32
Stride: 16
FillSize: 48
- Name: ExpectedOut
Format: UInt32
Stride: 4
Data: [3221225471, 0, 0, 0, 65535, 0, 0, 0, 0, 0, 0, 0]
Results:
- Result: Test
Rule: BufferExact
Actual: Out
Expected: ExpectedOut
DescriptorSets:
- Resources:
- Name: Out
Kind: RWStructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
...
#--- end

# REQUIRES: WaveSize_32

# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
115 changes: 56 additions & 59 deletions test/WaveOps/WaveActiveBallot.Wave64.test
Original file line number Diff line number Diff line change
@@ -1,59 +1,56 @@
#--- source.hlsl
RWStructuredBuffer<uint4> Out : register(u1);

[WaveSize(64)]
[numthreads(64, 1, 1)]
void main(uint3 threadID : SV_DispatchThreadID) {
// We expect the first and second resulting uint's bitmask to be
// 0xBFFFFFFF
Out[0] = WaveActiveBallot(threadID.x != 30 && threadID.x != 62);

// We expect the first resulting uint's bitmask to be
// 0x0000FFFF, and the second to be 0xFFFF0000
Out[1] = WaveActiveBallot(threadID.x < 16 || threadID.x > 47 );

// We expect the resulting uint4 to be 4 0x00000000's
Out[2] = WaveActiveBallot(false);
}

//--- pipeline.yaml

---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: Out
Format: UInt32
Stride: 4
FillSize: 48
- Name: ExpectedOut
Format: UInt32
Stride: 4
Data: [3221225471, 3221225471, 0, 0, 65535, 4294901760, 0, 0, 0, 0, 0, 0]
Results:
- Result: Test
Rule: BufferExact
Actual: Out
Expected: ExpectedOut
DescriptorSets:
- Resources:
- Name: Out
Kind: RWStructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
...
#--- end

# REQUIRES: WaveSize_64

# Bug: https://github.com/llvm/offload-test-suite/issues/688
# XFAIL: AMD && DirectX

# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
#--- source.hlsl
RWStructuredBuffer<uint4> Out : register(u1);

[WaveSize(64)]
[numthreads(64, 1, 1)]
void main(uint3 threadID : SV_DispatchThreadID) {
// We expect the first and second resulting uint's bitmask to be
// 0xBFFFFFFF
Out[0] = WaveActiveBallot(threadID.x != 30 && threadID.x != 62);

// We expect the first resulting uint's bitmask to be
// 0x0000FFFF, and the second to be 0xFFFF0000
Out[1] = WaveActiveBallot(threadID.x < 16 || threadID.x > 47 );

// We expect the resulting uint4 to be 4 0x00000000's
Out[2] = WaveActiveBallot(false);
}

//--- pipeline.yaml

---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: Out
Format: UInt32
Stride: 16
FillSize: 48
- Name: ExpectedOut
Format: UInt32
Stride: 4
Data: [3221225471, 3221225471, 0, 0, 65535, 4294901760, 0, 0, 0, 0, 0, 0]
Results:
- Result: Test
Rule: BufferExact
Actual: Out
Expected: ExpectedOut
DescriptorSets:
- Resources:
- Name: Out
Kind: RWStructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
...
#--- end

# REQUIRES: WaveSize_64

# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_6 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
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