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278 changes: 237 additions & 41 deletions lib/API/VK/Device.cpp

Large diffs are not rendered by default.

75 changes: 75 additions & 0 deletions test/Feature/Sparse/SparseByteAddressBuffer.test
Original file line number Diff line number Diff line change
@@ -0,0 +1,75 @@
#--- source.hlsl
RWByteAddressBuffer X : register(u0);
RWStructuredBuffer<int> Out : register(u1);

[numthreads(1,1,1)]
void main() {
// Index 0: Offset 0.
Out[0] = X.Load(0);

// Offset 128000: Second tile.
Out[1] = X.Load(128000);
}

//--- pipeline.yaml
---

Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: X
Format: Int32
Stride: 4
FillSize: 131072
FillValue: 9001
- Name: Out
Format: Int32
Stride: 4
FillSize: 8
FillValue: 0
- Name: ExpectedOut
Format: Int32
Stride: 4
Data: [9001, 0]

Results:
- Result: Test
Rule: BufferExact
Actual: Out
Expected: ExpectedOut

DescriptorSets:
- Resources:
- Name: X
Kind: RWByteAddressBuffer
IsReserved: true
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
TilesMapped: 1
- Name: Out
Kind: RWStructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
#--- end

# REQUIRES: !Vulkan || sparseBinding
# REQUIRES: !Vulkan || sparseResidencyBuffer

# XFAIL: Clang

# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o | FileCheck %s

# CHECK: - Name: Out
# CHECK-NEXT: Format: Int32
# CHECK-NEXT: Stride: 4
# CHECK-NEXT: Data: [ 9001, 0 ]
76 changes: 76 additions & 0 deletions test/Feature/Sparse/SparseRWStructuredBuffer.test
Original file line number Diff line number Diff line change
@@ -0,0 +1,76 @@
#--- source.hlsl
RWStructuredBuffer<int> X : register(u0);
RWStructuredBuffer<int> Out : register(u1);

[numthreads(1,1,1)]
void main() {
// Index 0: Guaranteed to be in the first mapped tile.
Out[0] = X[0];

// Index 32000: 32000 * 4 bytes = 128,000 bytes.
// If tile size is 64KB (65536 bytes), this is in the second tile (offset 65536+).
// This should return 0 because it is unmapped.
Out[1] = X[32000];
}

//--- pipeline.yaml
---

Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: X
Format: Int32
Stride: 4
FillSize: 131072 # 128KB total bytes (32768 elements)
FillValue: 9001
- Name: Out
Format: Int32
Stride: 4
FillSize: 8
FillValue: 0
- Name: ExpectedOut
Format: Int32
Stride: 4
Data: [9001, 0]

Results:
- Result: Test
Rule: BufferExact
Actual: Out
Expected: ExpectedOut

DescriptorSets:
- Resources:
- Name: X
Kind: RWStructuredBuffer
IsReserved: true
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
TilesMapped: 1
- Name: Out
Kind: RWStructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
#--- end

# REQUIRES: !Vulkan || sparseBinding
# REQUIRES: !Vulkan || sparseResidencyBuffer
# REQUIRES: !Vulkan || residencyNonResidentStrict

# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o | FileCheck %s

# CHECK: - Name: Out
# CHECK-NEXT: Format: Int32
# CHECK-NEXT: Stride: 4
# CHECK-NEXT: Data: [ 9001, 0 ]
83 changes: 83 additions & 0 deletions test/Feature/Sparse/SparseStructuredBuffer.test
Original file line number Diff line number Diff line change
@@ -0,0 +1,83 @@
#--- source.hlsl
RWBuffer<int> X : register(u0);
RWStructuredBuffer<int> Out : register(u1);

[numthreads(1,1,1)]
void main() {
// Index 0: Guaranteed to be in the first mapped tile.
Out[0] = X[0];

// Index 32000: 32000 * 4 bytes = 128,000 bytes.
// If tile size is 64KB (65536 bytes), this is in the second tile (offset 65536+).
// This should return 0 since it is unmapped.
Out[1] = X[32000];
}

//--- pipeline.yaml
---

Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: X
Format: Int32
Stride: 4
FillSize: 131072 # 128KB total bytes (32768 elements)
FillValue: 9001
- Name: Out
Format: Int32
Stride: 4
FillSize: 8
FillValue: 0
- Name: ExpectedOut
Format: Int32
Stride: 4
Data: [9001, 0]

Results:
- Result: Test
Rule: BufferExact
Actual: Out
Expected: ExpectedOut

DescriptorSets:
- Resources:
- Name: X
Kind: RWBuffer
IsReserved: true
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
TilesMapped: 1
- Name: Out
Kind: RWStructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
#--- end

# REQUIRES: !Vulkan || sparseBinding
# REQUIRES: !Vulkan || sparseResidencyBuffer
# REQUIRES: !Vulkan || residencyNonResidentStrict

# RUN: split-file %s %t

# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl

# RUN: %offloader %t/pipeline.yaml %t.o | FileCheck %s



# CHECK: - Name: Out

# CHECK-NEXT: Format: Int32

# CHECK-NEXT: Stride: 4

# CHECK-NEXT: Data: [ 9001, 0 ]
67 changes: 67 additions & 0 deletions test/Feature/Sparse/SparseTypedLoad.test
Original file line number Diff line number Diff line change
@@ -0,0 +1,67 @@
#--- source.hlsl
Buffer<int4> X : register(t0);

RWStructuredBuffer<int> Out : register(u1);

[numthreads(1,1,1)]
void main() {
int4 Result;

// Index 0: Tile 0 of X. Mapped.
Result = X.Load(0);
Out[0] = Result.x;

// Index 5000: Tile 1 of X. Unmapped.
Result = X.Load(5000);
Out[1] = Result.x;
}

//--- pipeline.yaml
---

Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: X
Format: Int32
Channels: 4
FillSize: 131072 # 128KB
FillValue: 9001
- Name: Out
Format: Int32
Stride: 4
FillSize: 8
DescriptorSets:
- Resources:
- Name: X
Kind: Buffer
IsReserved: true
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
TilesMapped: 1
- Name: Out
Kind: RWStructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
#--- end

# REQUIRES: !Vulkan || sparseBinding
# REQUIRES: !Vulkan || sparseResidencyBuffer
# REQUIRES: !Vulkan || residencyNonResidentStrict

# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o | FileCheck %s

# CHECK: - Name: Out
# CHECK-NEXT: Format: Int32
# CHECK-NEXT: Stride: 4
# CHECK-NEXT: Data: [ 9001, 0 ]
60 changes: 60 additions & 0 deletions test/Feature/Sparse/SparseTypedLoadMapped.test
Original file line number Diff line number Diff line change
@@ -0,0 +1,60 @@
#--- source.hlsl
Buffer<int4> X : register(t0);
RWStructuredBuffer<int> Out : register(u1);

[numthreads(1,1,1)]
void main() {
// Index 0: Tile 0. Mapped.
Out[0] = X.Load(0).x;
// Index 5000: Tile 1 (offset 80000). Mapped (TilesMapped: 2 = 128KB).
Out[1] = X.Load(5000).x;
}

//--- pipeline.yaml
---

Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: X
Format: Int32
Channels: 4
FillSize: 131072
FillValue: 9001
- Name: Out
Format: Int32
Stride: 4
FillSize: 8
DescriptorSets:
- Resources:
- Name: X
Kind: Buffer
IsReserved: true
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
TilesMapped: 2
- Name: Out
Kind: RWStructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
#--- end

# REQUIRES: !Vulkan || sparseBinding
# REQUIRES: !Vulkan || sparseResidencyBuffer

# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o | FileCheck %s

# CHECK: - Name: Out
# CHECK-NEXT: Format: Int32
# CHECK-NEXT: Stride: 4
# CHECK-NEXT: Data: [ 9001, 9001 ]
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