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Kitoc/vls cc #1

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333487e
Use gimple_call_fntype rather than gimple_call_fndecl in pass_return_…
kito-cheng Jul 31, 2025
94ff841
RISC-V: Allow VLS types using up to LMUL 8
kito-cheng Jul 31, 2025
1f387e2
RISC-V: Fix can_find_related_mode_p for VLS type
kito-cheng Aug 14, 2025
4bd2d40
Increase the NUM_ABI_IDS to 12
kito-cheng Aug 8, 2025
c032f20
RISC-V: Implement TARGET_[FUNCTION_VALUE|LIBCALL_VALUE] rather than […
kito-cheng Aug 8, 2025
a4c7302
RISC-V: Adding testsuite for VLS CC
kito-cheng Aug 13, 2025
7ed5d27
RISC-V: Implment VLS-CC
kito-cheng Aug 8, 2025
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4 changes: 2 additions & 2 deletions gcc/config/riscv/riscv-protos.h
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Original file line number Diff line number Diff line change
Expand Up @@ -763,7 +763,7 @@ opt_machine_mode vectorize_related_mode (machine_mode, scalar_mode,
unsigned int autovectorize_vector_modes (vec<machine_mode> *, bool);
bool cmp_lmul_le_one (machine_mode);
bool cmp_lmul_gt_one (machine_mode);
bool vls_mode_valid_p (machine_mode);
bool vls_mode_valid_p (machine_mode, bool allow_up_to_lmul_8 = true);
bool vlmax_avl_type_p (rtx_insn *);
bool has_vl_op (rtx_insn *);
bool tail_agnostic_p (rtx_insn *);
Expand Down Expand Up @@ -830,7 +830,7 @@ extern bool th_print_operand_address (FILE *, machine_mode, rtx);

extern bool strided_load_broadcast_p (void);
extern bool riscv_use_divmod_expander (void);
void riscv_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree, int);
void riscv_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx, tree, int);
extern bool
riscv_option_valid_attribute_p (tree, tree, tree, int);
extern bool
Expand Down
78 changes: 78 additions & 0 deletions gcc/config/riscv/riscv-selftests.cc
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Expand Up @@ -367,6 +367,83 @@ run_broadcast_selftests (void)
BROADCAST_TEST (MODE_VECTOR_FLOAT)
}

static void
test_vectorize_related_mode (machine_mode vec_mode, scalar_mode ele_mode,
machine_mode expected)
{
opt_machine_mode result = riscv_vector::vectorize_related_mode (vec_mode, ele_mode, 0);
machine_mode result_mode = result.require ();
printf ("%s %s %s %s\n", mode_name[result_mode], mode_name[vec_mode], mode_name[ele_mode], mode_name[expected]);
ASSERT_TRUE (result == expected);
}

static void
run_vectorize_related_mode_selftests (void)
{
riscv_selftest_arch_abi_setter rv ("rv64imafdcv", ABI_LP64D);
enum rvv_max_lmul_enum backup_rvv_max_lmul = rvv_max_lmul;
rvv_max_lmul = RVV_M1;
test_vectorize_related_mode ( V32QImode, QImode, V16QImode);
test_vectorize_related_mode ( V32QImode, HImode, V8HImode);
test_vectorize_related_mode ( V32QImode, SImode, V4SImode);
test_vectorize_related_mode ( V32QImode, DImode, V2DImode);

test_vectorize_related_mode (RVVM1QImode, SImode, RVVM1SImode);
test_vectorize_related_mode (RVVM2QImode, SImode, RVVM1SImode);
test_vectorize_related_mode (RVVM4QImode, SImode, RVVM1SImode);
test_vectorize_related_mode (RVVM8QImode, SImode, RVVM1SImode);
test_vectorize_related_mode (RVVM8QImode, DImode, RVVM1DImode);
test_vectorize_related_mode (RVVM8QImode, QImode, RVVM1QImode);
test_vectorize_related_mode (RVVM8QImode, HImode, RVVM1HImode);

rvv_max_lmul = RVV_M2;

test_vectorize_related_mode ( V32QImode, QImode, V32QImode);
test_vectorize_related_mode ( V32QImode, HImode, V16HImode);
test_vectorize_related_mode ( V32QImode, SImode, V8SImode);
test_vectorize_related_mode ( V32QImode, DImode, V4DImode);

test_vectorize_related_mode (RVVM1QImode, SImode, RVVM2SImode);
test_vectorize_related_mode (RVVM2QImode, SImode, RVVM2SImode);
test_vectorize_related_mode (RVVM4QImode, SImode, RVVM2SImode);
test_vectorize_related_mode (RVVM8QImode, SImode, RVVM2SImode);
test_vectorize_related_mode (RVVM8QImode, DImode, RVVM2DImode);
test_vectorize_related_mode (RVVM8QImode, QImode, RVVM2QImode);
test_vectorize_related_mode (RVVM8QImode, HImode, RVVM2HImode);

rvv_max_lmul = RVV_M4;

test_vectorize_related_mode ( V128QImode, QImode, V64QImode);
test_vectorize_related_mode ( V128QImode, HImode, V32HImode);
test_vectorize_related_mode ( V128QImode, SImode, V16SImode);
test_vectorize_related_mode ( V128QImode, DImode, V8DImode);

test_vectorize_related_mode (RVVM1QImode, SImode, RVVM4SImode);
test_vectorize_related_mode (RVVM2QImode, SImode, RVVM4SImode);
test_vectorize_related_mode (RVVM4QImode, SImode, RVVM4SImode);
test_vectorize_related_mode (RVVM8QImode, SImode, RVVM4SImode);
test_vectorize_related_mode (RVVM8QImode, DImode, RVVM4DImode);
test_vectorize_related_mode (RVVM8QImode, QImode, RVVM4QImode);
test_vectorize_related_mode (RVVM8QImode, HImode, RVVM4HImode);

rvv_max_lmul = RVV_M8;

test_vectorize_related_mode ( V128QImode, QImode, V128QImode);
test_vectorize_related_mode ( V128QImode, HImode, V64HImode);
test_vectorize_related_mode ( V128QImode, SImode, V32SImode);
test_vectorize_related_mode ( V128QImode, DImode, V16DImode);

test_vectorize_related_mode (RVVM1QImode, SImode, RVVM4SImode);
test_vectorize_related_mode (RVVM2QImode, SImode, RVVM8SImode);
test_vectorize_related_mode (RVVM4QImode, SImode, RVVM8SImode);
test_vectorize_related_mode (RVVM8QImode, SImode, RVVM8SImode);
test_vectorize_related_mode (RVVM8QImode, DImode, RVVM8DImode);
test_vectorize_related_mode (RVVM8QImode, QImode, RVVM8QImode);
test_vectorize_related_mode (RVVM8QImode, HImode, RVVM8HImode);

rvv_max_lmul = backup_rvv_max_lmul;
}

namespace selftest {
/* Run all target-specific selftests. */
void
Expand All @@ -387,6 +464,7 @@ riscv_run_selftests (void)
run_poly_int_selftests ();
run_const_vector_selftests ();
run_broadcast_selftests ();
run_vectorize_related_mode_selftests ();
}
} // namespace selftest
#endif /* #if CHECKING_P */
33 changes: 17 additions & 16 deletions gcc/config/riscv/riscv-v.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -2910,7 +2910,7 @@ autovectorize_vector_modes (vector_modes *modes, bool)
machine_mode mode;
while (size > 0 && get_vector_mode (QImode, size).exists (&mode))
{
if (vls_mode_valid_p (mode))
if (vls_mode_valid_p (mode, /* allow_up_to_lmul_8 */ false))
modes->safe_push (mode);

i++;
Expand Down Expand Up @@ -2954,7 +2954,7 @@ can_find_related_mode_p (machine_mode vector_mode, scalar_mode element_mode,
GET_MODE_SIZE (element_mode), nunits))
return true;
if (riscv_v_ext_vls_mode_p (vector_mode)
&& multiple_p (TARGET_MIN_VLEN * TARGET_MAX_LMUL,
&& multiple_p ((TARGET_MIN_VLEN * TARGET_MAX_LMUL) / 8,
GET_MODE_SIZE (element_mode), nunits))
return true;
return false;
Expand Down Expand Up @@ -5027,26 +5027,27 @@ cmp_lmul_gt_one (machine_mode mode)
Then we can have the condition for VLS mode in fixed-vlmax, aka:
PRECISION (VLSmode) < VLEN / (64 / PRECISION(VLS_inner_mode)). */
bool
vls_mode_valid_p (machine_mode vls_mode)
vls_mode_valid_p (machine_mode vls_mode, bool allow_up_to_lmul_8)
{
if (!TARGET_VECTOR || TARGET_XTHEADVECTOR)
return false;

if (rvv_vector_bits == RVV_VECTOR_BITS_SCALABLE)
{
if (GET_MODE_CLASS (vls_mode) != MODE_VECTOR_BOOL
&& !ordered_p (TARGET_MAX_LMUL * BITS_PER_RISCV_VECTOR,
GET_MODE_PRECISION (vls_mode)))
/* We enable VLS modes which are aligned with TARGET_MAX_LMUL and
BITS_PER_RISCV_VECTOR.

e.g. When TARGET_MAX_LMUL = 1 and BITS_PER_RISCV_VECTOR = (128,128).
We enable VLS modes have fixed size <= 128bit. Since ordered_p is
false between VLA modes with size = (128, 128) bits and VLS mode
with size = 128 bits, we will end up with multiple ICEs in
middle-end generic codes. */
return false;
return true;
if (GET_MODE_CLASS (vls_mode) != MODE_VECTOR_BOOL)
return true;
if (allow_up_to_lmul_8)
return true;
/* We enable VLS modes which are aligned with TARGET_MAX_LMUL and
BITS_PER_RISCV_VECTOR.

e.g. When TARGET_MAX_LMUL = 1 and BITS_PER_RISCV_VECTOR = (128,128).
We enable VLS modes have fixed size <= 128bit. Since ordered_p is
false between VLA modes with size = (128, 128) bits and VLS mode
with size = 128 bits, we will end up with multiple ICEs in
middle-end generic codes. */
return !ordered_p (TARGET_MAX_LMUL * BITS_PER_RISCV_VECTOR,
GET_MODE_PRECISION (vls_mode));
}

if (rvv_vector_bits == RVV_VECTOR_BITS_ZVL)
Expand Down
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